Data Sheet

Ethernet Controller I210 — Programming Interface
394
1
These bits are read from the Flash.
2
These bits also reset when PCIe resets.
This register provides software direct access to the Flash. Software can control the Flash by successive
writes to this register. Data and address information is clocked into the Flash by software toggling the
FL_SCK bit (bit 0) of this register with FL_CE set to 0b. Data output from the Flash is latched into the
FL_SO bit (bit 3) of this register via the internal 125 MHz clock and can be accessed by software via
reads of this register.
FL_SO (RO) 3 0b
Data Output Bit From Flash. The FL_SO input signal is mapped directly to this bit in the
register and contains the Flash serial data output. This bit is read-only from a software
perspective. Note that writes to this bit have no effect. RO bit.
FL_REQ 4 0b
2
Request Flash Access. Software must write a 1b to this bit to get direct Flash access. It
has access when FL_GNT is set to 1b. When software completes the access, it must
then write a 0b.
This bit is not operational by the host when in the Flash Secure mode.
FL_GNT (RO) 5 0b
Grant Flash Access. When this bit is set to 1b, software can access the Flash using the
FL_SCK, FL_CE, FL_SI, and FL_SO bits.
LOCKED (RO) 6 0b
A bit indicating (when set to 1b) that the Flash is in Secure mode.
When set to 0b, the Flash is in Non-secure mode.
FLA_ABORT (RO) 7 0b
2
Bit is set by hardware when Flash access was aborted due to the deadlock avoidance.
When this bit is set, further Flash bit banging access from this function is blocked.
Note: This bit is cleared by a write of 1b to the FLA.FLA_CLR_ERR bit.
FLA_CLR_ERR (SC) 8 0b
Clear Flash Access Error.
A write of 1b to this bit clears the FLA.FLA_ABORT bit and enables further bit banging
access to the Flash.
Reserved 15:9 0b Reserved. Reads as 0b.
EIP (RO) 16 0b Sector Erase In Progress. Indicates that the Flash is in a sector erase cycle. RO bit.
FL_SIZE (RO) 19:17 000b
1
Flash Size. Indicates the size of the Flash device according to the following equation:
Size = 64 KB * 2 ** “FL_SIZE”.
The Flash size limits the range host memory mapped flash accesses and of Expansion
ROM BAR mapped accesses to the Expansion ROM module beginning up to the Flash
device’s end.
Supported Flash sizes:
000b = 0 - no valid Flash contents or no Flash device.
101b = 2 MB.
110b = 4 MB.
111b = 8 MB.
This field is written by hardware from Flash words 0x11 after LAN_POWER_GOOD.
Reserved 28:20 0x0 Reserved.
FLASH_BUSY (RO) 29 0b
This bit indicates that the Flash is busy processing a Flash transaction and should not be
accessed.
FL_BAR_BUSY (RO) 30 0b BAR write can be done only while this bit is set to 0b.
Reserved 31 0b Reserved.
Field Bit(s) Init. Description