Data Sheet

Programming Interface — Ethernet Controller I210
393
8.4.5 EEPROM Load Control Register - EELOADCTL (0x12020; RW)
This register is used by software to control I211 auto-read operation and to execute EEPROM auto-read
sequences mimicking occurrence of various resets.
Note: Register reset by LAN_PWR_GOOD only.
8.4.6 EEPROM-Mode Write Register – EEWR (0x12018; RW)
This register is used by software to write individual words in the internal shadow RAM that is about to
reflect the first valid 4 KB sector of the Flash. To write a word, software writes the address to the Write
Address field and the data to the Write Data field. The I210 writes the word into the internal shadow
RAM, setting the Write Done field to 1b. Software can poll this register, looking for a 1b in the Write
Done field before the next write. The data is effectively copied into the Flash device by use of the
EEC.FLUPD command.
When this register is used to write a word into the Flash, that word is not written to any of the I210's
internal registers even if it is normally a hardware-accessed word.
8.4.7 Flash Access - FLA (0x1201C; RW)
This register provides software direct access to the Flash. Software can control the Flash by successive
writes to this register. Data and address information is clocked into the Flash by software toggling the
FL_SCK in this register. Data output from the Flash is latched into bit 3 of this register via the internal
125 MHz clock and can be accessed by software via reads of this register.
Field Bit(s) Init. Description
CMDV (RO) 0 0b
Command Valid.
This bit is cleared by hardware in case the write request was rejected.
DONE (RO field) 1 1b
Write Done.
Set this bit to 1b when the EEPROM-mode write completes.
Set this bit to 0b when the EEPROM-mode write is in progress.
Note that writes by software are ignored.
ADDR 12:2 0x0
Write Address.
This field is written by software to indicate the address of the word to write.
Reserved 15:13 0x0 Reserved. Reads as 0x0.
DATA 31:16 0x0
Write Data.
Data to be written into the shadow RAM.
Field Bit(s) Init. Description
FL_SCK 0 0b
2
Clock Input to Flash. When FL_GNT is set to 1b, the FL_SCK output signal is mapped to
this bit and provides the serial clock input to the Flash. Software clocks the Flash via
toggling this bit with successive writes.
This bit is not operational by the host when in the Flash Secure mode.
FL_CS 1 1b
2
Chip Select Input to Flash. When FL_GNT is set to 1b, the FL_CS output signal is
mapped to the chip select of the Flash device. Software enables the Flash by writing a
0b to this bit.
This bit is not operational by the host when in the Flash Secure mode.
FL_SI 2 0b
2
Data Input to Flash. When FL_GNT is set to 1b, the FL_SI output signal is mapped
directly to this bit. Software provides data input to the Flash via writes to this bit.
This bit is not operational by the host when in the Flash Secure mode.