Data Sheet

Programming Interface — Ethernet Controller I210
391
8.4.3 EEPROM-Mode Read Register - EERD (0x12014; RW)
This register is used by software to read individual words from the internal shadow RAM that reflects
the first valid 4 KB sector of the Flash. To read a word, software writes the address to the Read Address
field. Writing the register sets the Done bit to 0b. The I210 then reads the word from the internal
shadow RAM and places it in the Read Data field, setting the Read Done field to 1b. Software can poll
this register, looking for a 1b in the Read Done field and then using the value in the Read Data field.
This register is used by software to cause the I210 to read individual words in the EEPROM. To read a
word, software writes the address to the Read Address field and simultaneously writes a 1b to the Start
Read field. The I211 reads the word from the EEPROM and places it in the Read Data field, setting the
Read Done field to 1b. Software can poll this register, looking for a 1b in the Read Done field, and then
using the value in the Read Data field.
EE_SIZE (RO) 14:11
2
0111b
EEPROM Size
This field defines the size of the EEPROM:
Field Value EEPROM Size EEPROM Address Size
0111b 16 Kbytes 2 bytes
1000b 32 Kbytes 2 bytes
Note:
EE_BLOCKED (RO) 15 0b
EEPROM access blocked
EEPROM Bit Banging access blocked - Bit is set by HW when detecting an
EEPROM access violation during bit banging access using the EEC register or
detecting an EEPROM access violation when accessing the EPROM using the
EERD register. When bit is set further Bit Banging operations from the function
are disabled until bit is cleared.
Type of violations that can cause the bit to be set are write to read-only sections,
access to a hidden area or any other EEPROM protection violation detected.
Note: Bit is cleared by write one to the EEC.EE_CLR_ERR bit.
EE_ABORT (RO) 16 0b
EEPROM access Aborted
Bit is set by HW when EEPROM access was aborted due to deadlock avoidance,
management reset or EEPROM reset via CTRL_EXT.EE_RST.
When bit is set further Bit Banging operations from the Function are disabled
until bit is cleared.
Note: Bit is cleared by write one to the EEC.EE_CLR_ERR bit.
EE_RD_TIMEOUT
(RO)
17 0b
EERD access timeout
When bit is set to 1b indicates the EEPROM access via EERD register timed out
while trying to read EEPROM status (Can occur when no EEPROM exists).
Note: Bit is cleared by write one to the EEC.EE_CLR_ERR bit.
EE_CLR_ERR (SC) 18 0b
Clear EEPROM Access Error
A write 1b to the EE_CLR_ERR bit clears the EEC.EE_ABORT bit, EE_BLOCKED
bit and EE_RD_TIMEOUT bit.
Note: Clearing the EEC.EE_ABORT bit and EE_BLOCKED bit enables further Bit
Banging access to the EEPROM from the function.
EE_DET (RO) 19 X
EEPROM Detected
Note: Bit is set to 1b when EEPROM responded correctly to a get status
opcode following power-up.
Reserved 31:20 0x0
Reserved
Write 0 ignore on read.
1. Value depends on voltage level on EE_DO pin following initialization
2. These bits are read from the Flash.
Field Bit(s) Initial Value Description