Data Sheet

Ethernet Controller I210 — Programming Interface
388
8.3 Internal Packet Buffer Size Registers
The following registers define the size of the on-chip receive and transmit buffers used to receive and
transmit packets. Refer to Section 4.6.9 for the general setting rule that applies on all these packet
buffers.
The registers in this chapter reset only on power up.
8.3.1 RX Packet Buffer Size - RXPBSIZE (0x2404; R/W)
8.3.2 TX Packet Buffer Size - TXPBSIZE (0x3404; R/W)
8.4 Flash Registers Descriptions
8.4.1 EEPROM-Mode Control Register - EEC (0x12010; RW)
This register provides software direct access to the Flash.
Reserved 27:24 0000b Reserved.
Reserved 29:28 0x0
Reserved.
Write 0x0, ignore on read.
Reserved 31:30 00b Reserved.
1. These bits are read from the Flash.
Field Bit(s) Init. Description
Rxpbsize 5:0 0x22 Rx packet buffer size in KB.
Bmc2ospbsize 11:6 0x02 BMC to OS packet buffer size in KB.
Reserved 30:12 0x0
Reserved.
Write 0b, ignore on read.
cfg_ts_en 31 0x0
If set, a line is saved (16 bytes) per packet in the Rx packet buffer for the timestamp
descriptor.
If not set, no timestamp in packet support.
Field Bit(s) Init, Description
Txpb0size 5:0 0x14
Tx Packet Buffer 0 Size in KB.
In Qav mode, it controls the size in KB of the TXPB0, which is associated to TxQ0.
Txpb1size 11:6 0x0
In Qav mode, it controls the size in KB of the TXPB1, which is associated to TxQ1.
Txpb2size 17:12 0x0
In Qav mode, it controls the size in KB of the TXPB2, which is associated to TxQ2.
Txpb3size 23:18 0x0
In Qav mode, it controls the size in KB of the TXPB3, which is associated to TxQ3.
os2Bmcpbsize 29:24 0x4 OS to BMC packet buffer size in KB.
Reserved 31:30 0x0
Reserved
Write 0b, ignore on read.
Field Bit(s)
Initial
Value
Description