Data Sheet

Programming Interface — Ethernet Controller I210
383
The I210 enables up to four externally controlled interrupts. All software-definable pins, these can be
mapped for use as GPI interrupt bits. Mappings are enabled by the SDPx_GPIEN bits only when these
signals are also configured as inputs via SDPx_IODIR. When configured to function as external interrupt
pins, a GPI interrupt is generated when the corresponding pin is sampled in an active-high state.
RO_DIS 17 0b
Relaxed Ordering Disabled
When set to 1b, the I210 does not request any relaxed ordering
transactions on the PCIe interface regardless of the state of bit 4 in the
PCIe Device Control register. When this bit is cleared and bit 4 of the PCIe
Device Control register is set, the I210 requests relaxed ordering
transactions as specified by registers RXCTL and TXCTL (per queue and per
flow).
SerDes Low
Power Enable
18 0b
1
When set, enables the SerDes to enter a low power state when the function
is in Dr state .
Dynamic MAC
Clock Gating
19 0b
1
When set, enables dynamic MAC clock gating.
PHY Power
Down Enable
20 1b
1
When set, enables the PHY to enter a low-power state as described in
Section 5.4.2.
Reserved 21 0b
Reserved.
Write 0b, ignore on read.
LINK_MODE 23:22 0x0
1
Link Mode
Controls interface on the link.
00b = Direct copper (1000Base-T) interface (10/100/1000 BASE-T internal
PHY mode).
01b = 1000BASE-KX.
10b = SGMII.
11b = SerDes interface.
Note:
1. This bit is reset only on power-up or PCIe reset.
Reserved 24 0b
Reserved.
Write 0b, ignore on read.
I2C Enabled 25 0b
1
Enable I
2
C
This bit enables the SFPx_I2C pins that can be used to access external SFP
modules or an external 1000BASE-T PHY via the MDIO interface. If cleared,
the SFPx_I2C pads are isolated and accesses to the SFPx_I2C pins through
the I2CCMD register or the MDIC register are ignored.
EXT_VLAN 26 0b
1
External VLAN Enable
When set, all incoming Rx packets are expected to have at least one VLAN
with the Ether type as defined in VET.EXT_VET that should be ignored. The
packets can have a second internal VLAN that should be used for all
filtering purposes. All Tx packets are expected to have at least one VLAN
added to them by the host. In the case of an additional VLAN request (VLE
- VLAN Enable is set in transmit descriptor) the second VLAN is added after
the first external VLAN is added by the host. This bit is reset only by a
power up reset or by a full Flash auto load and should only be changed
while Tx and Rx processes are stopped.
Reserved 27 0b
Reserved.
Write 0b, ignore on read.
DRV_LOAD 28 0b
Driver Loaded
This bit should be set by the software device driver after it is loaded. This
bit should be cleared when the software device driver unloads or after a
PCIe reset. The Management controller reads this bit to indicate to the
manageability controller (BMC) that the driver has loaded.
Note: Bit is reset on power-up or PCIe reset only.
Reserved 31:29 0b
Reserved
Write 0b, Ignore on read.
1. These bits are read from the Flash.
Field Bit(s) Initial Value Description