Data Sheet

Ethernet Controller I210 — Programming Interface
382
Field Bit(s) Initial Value Description
Reserved 0 0b
Reserved.
Write 0b, ignore on read.
I2C over SDP
Enabled
10b
1
Enable I
2
C over SDP0 and SDP2 pins.
When set, SDP0 and SDP2 pins functions as an I
2
C interface operated
through the I2CCMD,I2CPARAMS register set.
SDP2_GPIEN 2 0b
General Purpose Interrupt Detection Enable for SDP2.
If software-controllable I/O pin SDP2 is configured as an input, this bit
(when set to 1b) enables use for GPI interrupt detection.
SDP3_GPIEN 3 0b
General Purpose Interrupt Detection Enable for SDP3.
If software-controllable I/O pin SDP3 is configured as an input, this bit
(when set to 1b) enables use for GPI interrupt detection.
Reserved 5:4 00b
Reserved.
Write 0b, ignore on read.
SDP2_DATA 6 0b
1
SDP2 Data Value. Used to read (write) the value of software-controllable I/
O pin SDP2. If SDP2 is configured as an output (SDP2_IODIR = 1b), this
bit controls the value driven on the pin (initial value Flash-configurable). If
SDP2 is configured as an input, reads return the current value of the pin.
SDP3_DATA 7 0b
1
SDP3 Data Value. Used to read (write) the value of software-controllable I/
O pin SDP3. If SDP3 is configured as an output (SDP3_IODIR = 1b), this
bit controls the value driven on the pin (initial value Flash-configurable). If
SDP3 is configured as an input, reads return the current value of the pin.
Reserved 9:8 0x0
1
Reserved.
Write 0b, ignore on read.
SDP2_IODIR 10 0b
1
SDP2 Pin Direction. Controls whether software-controllable pin SDP2 is
configured as an input or output (0b = input, 1b = output). Initial value is
Flash-configurable. This bit is not affected by software or system reset,
only by initial power-on or direct software writes.
SDP3_IODIR 11 0b
1
SDP3 Pin Direction. Controls whether software-controllable pin SDP3 is
configured as an input or output (0b = input, 1b = output). Initial value is
Flash-configurable. This bit is not affected by software or system reset,
only by initial power-on or direct software writes.
ASDCHK 12 0b
Auto-Speed-Detection (ASD) Check
Initiates an ASD sequence to sense the frequency of the PHY receive clock
(RX_CLK). The results are reflected in STATUS.ASDV. This bit is self-
clearing.
EE_RST (SC) 13 0b
EEPROM Block Reset
When set, initiates a reset-like event to the EEPROM block function. This
causes an Flash auto-load operation as if a software reset (CTRL.RST) had
occurred. This bit is self-clearing.
Reserved 14 0x0
Reserved.
Write 0b, ignore on read.
SPD_BYPS 15 0b
Speed Select Bypass
When set to 1b, all speed detection mechanisms are bypassed, and the
I210 is immediately set to the speed indicated by CTRL.SPEED. This
provides a method for software to have full control of the speed settings of
the I210 and when the change takes place, by overriding the hardware
clock switching circuitry.
NS_DIS 16 0
No Snoop Disable
When set to 1b, the I210 does not set the no snoop attribute in any PCIe
packet, independent of PCIe configuration and the setting of individual no
snoop enable bits. When set to 0b, behavior of no snoop is determined by
PCIe configuration and the setting of individual no snoop enable bits.