Data Sheet

Ethernet Controller I210 —Interconnects
38
• Disabling or enabling completion timeout.
• Disabling or enabling re-send of a request on completion timeout.
• A programmable range of re-sends on completion timeout, if re-send enabled.
• A programmable range of timeout values.
• Programming the behavior of completion timeout is listed in Table 3-3.
Completion Timeout Enable - Programmed through the PCI Device Control 2 configuration register. The
default is: Completion Timeout Enabled.
Resend Request Enable - The Completion Timeout Resend Flash bit (loaded to the
Completion_Timeout_Resend bit in the PCIe Control (GCR) register enables resending the request
(applies only when completion timeout is enabled). The default is to resend a request that timed out.
Number of re-sends on timeout - Programmed through the Number of resends field in the GCR register.
The default value of resends is 3.
3.1.3.2.1 Completion Timeout Period
Programmed through the PCI Device Control 2 configuration register (refer to Section 9.4.6.12). The
I210 supports all ranges defined by PCIe v2.1 (2.5GT/s).
A memory read request for which there are multiple completions are considered completed only when
all completions have been received by the requester. If some, but not all, requested data is returned
before the completion timeout timer expires, the requestor is permitted to keep or to discard the data
that was returned prior to timer expiration.
Note: The completion timeout value must be programmed correctly in PCIe configuration space (in
the Device Control 2 register); the value must be set above the expected maximum latency
for completions in the system in which the I210 is installed. This ensures that the I210
receives the completions for the requests it sends out, avoiding a completion timeout
scenario. It is expected that the system BIOS sets this value appropriately for the system.
3.1.4 Transaction Layer
The upper layer of the PCIe architecture is the transaction layer. The transaction layer connects to the
I210 core using an implementation specific protocol. Through this core-to-transaction-layer protocol,
the application-specific parts of the I210 interact with the PCIe subsystem and transmit and receive
requests to or from the remote PCIe agent, respectively.
Table 3-3. Completion Timeout Programming
Capability Programming capability
Completion Timeout Enabling Controlled through PCI Device Control 2 configuration register.
Resend Request Enable Loaded from the Flashinto the GCR register.
Number of Re-sends on Timeout Controlled through GCR register.
Completion Timeout Period Controlled through PCI Device Control 2 configuration register.