Data Sheet

Programming Interface — Ethernet Controller I210
381
8.2.3 Extended Device Control Register - CTRL_EXT (0x0018; R/W)
This register provides extended control of the I210’s functionality beyond that provided by the Device
Control (CTRL) register.
Reserved 5 X
Reserved.
Write 0b, ignore on read.
SPEED 7:6 X
Link Speed Setting
Reflects the speed setting of the MAC and/or link when it is operating in 10/
100/1000BASE-T mode (internal PHY).
When the MAC is operating in 10/100/1000BASE-T mode with the internal
PHY, these bits normally reflect the speed of the actual link, negotiated by
the PHY and link partner and reflected internally from the PHY to the MAC
(SPD_IND). These bits also might represent the speed configuration of the
MAC only, if the MAC speed setting has been forced via software
(CTRL.SPEED) or if MAC auto-speed detection is used.
If auto-speed detection is enabled, the I210's speed is configured only once
after the LINK signal is asserted by the PHY.
00b = 10 Mb/s.
01b = 100 Mb/s.
10b = 1000 Mb/s.
11b = 1000 Mb/s.
ASDV 9:8 X
Auto-Speed Detection Value
Speed result sensed by the I210’s MAC auto-detection function.
These bits are provided for diagnostics purposes only. The ASD calculation
can be initiated by software writing a logic 1b to the CTRL_EXT.ASDCHK
bit. The resultant speed detection is reflected in these bits.
Refer to Section 8.2.3 for details.
PHYRA 10 1b
PHY Reset Asserted
This read/write bit is set by hardware following the assertion of an internal
PHY reset; it is cleared by writing a 0b to it. This bit is also used by
firmware indicating a required initialization of the I210’s PHY.
Reserved 18:11 0x0
Reserved.
Write 0b, ignore on read.
GIO Master Enable
Status
19 1b
Cleared by the I210 when the CTRL.GIO Master Disable bit is set and no
master requests are pending by this function and is set otherwise. Indicates
that no master requests are issued by this function as long as the CTRL.GIO
Master Disable bit is set.
DEV_RST_SET (R/
W1C)
20 0b
Device Reset Set
When set, indicates that a device reset (CTRL.DEV_RST) was initiated by
one of the software drivers.
Note: Bit cleared by writing as 1b.
PF_RST_DONE 21 1b
PF _RST_DONE
When set, indicates that software reset (CTRL.RST) or device reset
(CTRL.DEV_RST) has completed and the software device driver can begin
initialization process.
Reserved 30:22 0x0
Reserved.
Write 0b, ignore on read.
MAC clock gating
Enable
31 0b
1
MAC Clock Gating Enable
This bit is loaded from the Flash indicating that the device supports MAC
clock. gating
1. If the signature bits of the Flash’s Initialization Control Word 1 match (01b), this bit is read from the Flash.
Field Bit(s) Initial Value Description