Data Sheet

Ethernet Controller I210 — Programming Interface
380
8.2.2 Device Status Register - STATUS (0x0008; RO)
DEV_RST
(SC)
29 0b
Device Reset
This bit performs a reset of the entire controller device, resulting in a state nearly
approximating the state following a power-up reset or internal PCIe reset, except for
system PCI configuration.
0b = Normal.
1b = Reset.
This bit is self clearing.
Notes:
1. Asserting DEV_RST generates an interrupt via the ICR.DRSTA interrupt bit.
2. Device Reset (CTRL.DEV_RST) can be used to globally reset the entire
component if the DEV_RST_EN bit in Initialization Control 4 Flash word is set.
3. Asserting DEV_RST sets the STATUS.DEV_RST_SET bit.
VME 30 0b
VLAN Mode Enable
When set to 1b, VLAN information is stripped from all received 802.1Q packets.
Note: If this bit is set, the RCTL.SECRC bit should also be set as the CRC is not valid
anymore.
PHY_RST 31 0b
PHY Reset
Generates a hardware-level reset to the internal 1000BASE-T PHY.
0b = Normal operation.
1b = Internal PHY reset asserted.
1. These bits are loaded from Flash.
Field Bit(s) Initial Value Description
FD 0 X
Full Duplex.
0b = Half duplex (HD).
1b = Full duplex (FD).
Reflects duplex setting of the MAC and/or link.
FD reflects the actual MAC duplex configuration. This normally reflects the
duplex setting for the entire link, as it normally reflects the duplex
configuration negotiated between the PHY and link partner (copper link) or
MAC and link partner (fiber link).
LU 1 X
Link up.
0b = No link established.
1b = Link established.
For this bit to be valid, the Set Link Up bit of the Device Control (CTRL.SLU)
register must be set.
Link up provides a useful indication of whether something is attached to the
port. Successful negotiation of features/link parameters results in link
activity. The link start-up process (and consequently the duration for this
activity after reset) can be several 100's of ms. When the internal PHY is
used, this reflects whether the PHY's LINK indication is present. When the
SerDes, SGMII or 1000BASE-KX interface is used, this indicates loss-of-
signal; if auto-negotiation is also enabled, this can also indicate successful
auto-negotiation. Refer to Section 3.7.4 for more details.
Note: This bit is valid only when working in internal PHY mode. In SerDes
mode bit is always 0b.
Reserved 3:2 X
Reserved
Write 0b, ignore on read.
TXOFF 4 X
Transmission Paused
This bit indicates the state of the transmit function when symmetrical flow
control has been enabled and negotiated with the link partner. This bit is set
to 1b when transmission is paused due to the reception of an XOFF frame.
It is cleared (0b) upon expiration of the pause timer or the receipt of an
XON frame.
Field Bit(s) Initial Value Description