Data Sheet

Programming Interface — Ethernet Controller I210
379
SDP0 DATA
(RWM)
18 0b
1
SDP0 Data Value
Used to read or write the value of software-controlled I/O pin SDP0.
If SDP0 is configured as an output (SDP0_IODIR = 1b), this bit controls the value
driven on the pin (initial value Flash-configurable).
If SDP0 is configured as an input, reads return the current value of the pin.
When the SDP0_WDE bit is set, this field indicates the polarity of the watchdog
indication.
Note:
SDP1 DATA
(RWM)
19 0b
1
SDP1 Data Value
Used to read or write the value of software-controlled I/O pin SDP1.
If SDP1 is configured as an output (SDP1_IODIR = 1b), this bit controls the value
driven on the pin (initial value Flash-configurable).
If SDP1 is configured as an input, reads return the current value of the pin.
Note:
ADVD3WUC 20 1b
1
D3Cold Wake up Capability Enable
When this bit is set to 0b, PME (WAKE#) is not generated in D3Cold.
Bit loaded from Flash (refer to Section 6.2.21).
SDP0_WDE 21 0b
1
SDP0 used for Watchdog Indication
When set, SDP0 is used as a watchdog indication. When set, the SDP0_DATA bit
indicates the polarity of the watchdog indication. In this mode, SDP0_IODIR must be
set to an output.
SDP0_IODIR 22 0b
1
SDP0 Pin Direction
Controls whether software-controllable pin SDP0 is configured as an input or output
(0b = input, 1b = output). Initial value is Flash-configurable. This bit is not affected by
software or system reset, only by initial power-on or direct software writes.
SDP1_IODIR 23 0b
1
SDP1 Pin Direction
Controls whether software-controllable pin SDP1 is configured as an input or output
(0b = input, 1b = output). Initial value is Flash-configurable. This bit is not affected by
software or system reset, only by initial power-on or direct software writes.
Reserved 25:24 0x0
Reserved.
Write 0b, ignore on read.
RST (SC) 26 0b
Port Software Reset
This bit performs a reset to the LAN port, resulting in a state nearly approximating the
state following a power-up reset or internal PCIe reset, except for system PCI
configuration and DMA logic.
0b = Normal.
1b = Reset.
This bit is self clearing and is referred to as software reset or global reset.
RFCE 27 1b
Receive Flow Control Enable
When set, indicates that the I210 responds to the reception of flow control packets. If
auto-negotiation is enabled, this bit is set to the negotiated flow control value.
In SerDes mode the resolution is done by the hardware. In internal PHY, SGMII or
1000BASE-KX modes it should be done by the software.
TFCE 28 0b
Transmit Flow Control Enable
When set, indicates that the I210 transmits flow control packets (XON and XOFF
frames) based on the receiver fullness. If auto-negotiation is enabled, this bit is set to
the negotiated duplex value.
In SerDes mode the resolution is done by the hardware. In internal PHY, SGMII or
1000BASE-KX modes it should be done by the software.
Field Bit(s) Initial Value Description