Data Sheet

Ethernet Controller I210 — Programming Interface
378
SLU 6 0b
1
Set Link Up
Set Link Up must be set to 1b to permit the MAC to recognize the LINK signal from the
PHY, which indicates the PHY has gotten the link up, and is ready to receive and
transmit data.
See Section 3.7.4 for more information about auto-negotiation and link configuration
in the various modes.
Notes:
1. The CTRL.SLU bit is normally initialized to 0b. However, if the APM Enable bit is
set in the Flash then it is initialized to 1b.
2. The CTRL.SLU bit is set to 1b if the Enable All Phys in D3 bit in the Common
Firmware Parameters 2 Flash word is set to 1b (See Section 6.7.1.3).
3. The CTRL.SLU bit is set in NC-SI mode according to the Enable Channel command
to the port.
4. In SerDes and 1000Base-KX modes Link up can be forced by setting this bit as
described in Section 3.7.4.1.4.
ILOS 7 0b
1
Invert Loss-of-Signal (LOS/LINK) Signal
This bit controls the polarity of the SRDS_[n]_SIG_DET signal or internal link-up
signal.
0b = Do not invert (active high input signal).
1b = Invert signal (active low input signal).
Notes:
1. Source of the link-up signal (SRDS_[n]_SIG_DET signal or internal link-up signal)
is set via the CONNSW.ENRGSRC bit. When using the internal link-up signal, this
bit should be set to 0b.
2. Should be set to 0b when using an internal copper PHY or when working in
SGMII, 1000BASE-BX or 1000BASE-KX modes.
SPEED 9:8 10b
Speed Selection.
These bits determine the speed configuration and are written by software after reading
the PHY configuration through the MDIO interface.
These signals are ignored when auto-speed detection is enabled.
00b = 10 Mb/s.
01b = 100 Mb/s.
10b = 1000 Mb/s.
11b = Not used.
Reserved 10 0b
Reserved.
Write 0b, ignore on read.
FRCSPD 11 0b
1
Force Speed
This bit is set when software needs to manually configure the MAC speed settings
according to the SPEED bits.
Note that MAC and PHY must resolve to the same speed configuration or software
must manually set the PHY to the same speed as the MAC.
Software must clear this bit to enable the PHY or ASD function to control the MAC
speed setting. Note that this bit is superseded by the CTRL_EXT.SPD_BYPS bit, which
has a similar function.
FRCDPLX 12 0b
Force Duplex
When set to 1b, software can override the duplex indication from the PHY that is
indicated in the FDX to the MAC. Otherwise, in 10/100/1000Base-T link mode, the
duplex setting is sampled from the PHY FDX indication into the MAC on the asserting
edge of the PHY LINK signal. When asserted, the CTRL.FD bit sets duplex.
Reserved 15:13 0x0
Reserved
Write 0b, ignore on read.
SDP0_GPIEN 16 0b
General Purpose Interrupt Detection Enable for SDP0
If software-controlled I/O pin SDP0 is configured as an input, this bit (when 1b)
enables the use for GPI interrupt detection.
SDP1_GPIEN 17 0b
General Purpose Interrupt Detection Enable for SDP1
If software-controlled I/O pin SDP1 is configured as an input, this bit (when 1b)
enables the use for GPI interrupt detection.
Field Bit(s) Initial Value Description