Data Sheet

Programming Interface — Ethernet Controller I210
377
8.1.3.1 Alias Addresses
Certain registers maintain an alias address designed for backward compatibility with software written
for previous GbE controllers. For these registers, the alias address is listed Table 8-6. Those registers
can be accessed by software at either the new offset or the alias offset. It is recommended that
software that is written solely for the I210, use the new address offset.
8.1.4 MSI-X BAR Register Summary
8.2 General Register Descriptions
8.2.1 Device Control Register - CTRL (0x00000; R/W)
This register, as well as the Extended Device Control (CTRL_EXT) register, controls the major
operational modes for the device. While software writes to this register to control device settings,
several bits (such as FD and SPEED) can be overridden depending on other bit settings and the
resultant link configuration determined by the PHY's auto-negotiation resolution. See Section 4.6.7 for
details on the setup of these registers in the different link modes.
Note: This register is also aliased at address 0x0004.
Table 8-7. MSI-X Register Summary
Category Offset Abbreviation Name RW Page
MSI-X Table
0x0000 + n*0x10
[n=0...4]
MSIXTADD
MSI–X Table Entry Lower
Address
RW page 432
MSI-X Table
0x0004 + n*0x10
[n=0...4]
MSIXTUADD
MSI–X Table Entry Upper
Address
RW page 432
MSI-X Table
0x0008 + n*0x10
[n=0...4]
MSIXTMSG MSI–X Table Entry Message R/W page 432
MSI-X Table
0x000C + n*0x10
[n=0...4]
MSIXTVCTRL
MSI–X Table Entry Vector
Control
R/W page 433
MSI-X Table 0x02000 MSIXPBA MSIXPBA Bit Description RO page 433
Field Bit(s) Initial Value Description
FD 0 1b
1
Full-Duplex
Controls the MAC duplex setting when explicitly set by software.
0b = Half duplex.
1b = Full duplex.
Reserved 1 0b
Reserved
Write 0b; ignore on read.
GIO Master
Disable
20b
When set to 1b, the function of this bit blocks new master requests including
manageability requests. If no master requests are pending by this function, the
STATUS.GIO Master Enable Status bit is set. See Section 5.2.3.3 for further
information.
Reserved 5:3 0x0
Reserved
Write 0b, ignore on read.