Data Sheet

Ethernet Controller I210 — Programming Interface
370
0x5008 N/A RFCTL Receive Filter Control Register RW
0x5200- 0x53FC
0x0200-
0x03FC
MTA[127:0] Multicast Table Array (n) RW
0x5400 + 8*n
0x0040 +
8*n
RAL[0-15] Receive Address Low (15:0) RW
0x5404 + 8 *n
0x0044 + 8
*n
RAH[0-15] Receive Address High (15:0) RW
0x5480 –
0x549C
N/A PSRTYPE[3:0] Packet Split Receive type (n) RW
0x5600-0x57FC
0x0600-
0x07FC
VFTA[127:0] VLAN Filter Table Array (n) RW
0x5818 N/A MRQC Multiple Receive Queues Command RW
0x5C00-0x5C7C N/A RETA Redirection Table RW
0x5C80-0x5CA4 N/A RSSRK RSS Random Key Register RW
0xC038 +
0x40*n
N/A DVMOLR[0 - 3] DMA VM Offload Register[0-3] RW
Transmit
0x0400 N/A TCTL Tx Control RW
0x0404 N/A TCTL_EXT Tx Control Extended RW
0x0410 N/A TIPG Tx IPG RW
0x041C N/A RETX_CTL Retry Buffer Control RW
0x3404 N/A TXPBSIZE Transmit Packet Buffer Size RW
0x359C N/A DTXTCPFLGL DMA Tx TCP Flags Control Low RW
0x35A0 N/A DTXTCPFLGH DMA Tx TCP Flags Control High RW
0x3540 N/A DTXMXSZRQ DMA Tx Max Total Allow Size Requests RW
0x355C N/A DTXMXPKTSZ DMA Tx Max Allowable Packet Size RW
0x3590 N/A DTXCTL DMA Tx Control RW
0x35A4 N/A DTXBCTL DMA Tx Behavior Control RW
0xE000
0x0420,
0x3800
TDBAL[0] Tx Descriptor Base Low 0 RW
0xE004
0x0424,
0x3804
TDBAH[0] Tx Descriptor Base High 0 RW
0xE008
0x0428,
0x3808
TDLEN[0] Tx Descriptor Ring Length 0 RW
0xE010
0x0430,
0x3810
TDH[0] Tx Descriptor Head 0 RO
0xE018
0x0438,
0x3818
TDT[0] Tx Descriptor Tail 0 RW
0xE028 0x3828 TXDCTL[0] Transmit Descriptor Control Queue 0 RW
0xE014 0x3814 TXCTL[0] Tx DCA CTRL Register Queue 0 RW
0xE038 0x3838 TDWBAL[0] Transmit Descriptor WB Address Low Queue 0 RW
0xE03C 0x383C TDWBAH[0] Transmit Descriptor WB Address High Queue 0 RW
0xE040 + 0x40
* (n-1)
0x3900 +
0x100 * (n-
1)
TDBAL[1-3] Tx Descriptor Base Low Queue 1 - 3 RW
0xE044 + 0x40
* (n-1)
0x3904 +
0x100 * (n-
1)
TDBAH[1-3] Tx Descriptor Base High Queue 1 - 3 RW
Table 8-6. Register Summary (Continued)
Offset Alias Offset Abbreviation Name RW