Data Sheet

Ethernet Controller I210 — Programming Interface

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PHY registers use a special nomenclature to define the read/write mode of individual bits in each

Note: For all binary equations appearing in the register map, the symbol “|” is equivalent to a binary

OR operation.

8.1.2.1 Registers Byte Ordering

This section defines the structure of registers that contain fields carried over the network. Some

examples are L2, L3 and L4 fields.

The following example is used to describe byte ordering over the wire (hex notation):

Last First

...,06, 05, 04, 03, 02, 01, 00

Each byte is sent with the LSbit first. That is, the bit order over the wire for this example is

Last First

..., 0000 0011, 0000 0010, 0000 0001, 0000 0000

The general rule for register ordering is to use host ordering (also called little Endian). Using the

previous example, a 6-byte fields (MAC address) is stored in a CSR in the following manner:

Byte 3 Byte 2 Byte 1 Byte0

DW address (N) 0x03 0x02 0x01 0x00

DW address (N+4) ... ... 0x05 0x04

RC/W1C

Read-only status, Write-1-to-clear status register: Read-to-clear status register. Register bits indicate status when

read, a set bit indicating a status event can be cleared by writing a 1b or by reading the register. Writing a 0b to RC/

W1C bit has no effect.

Read Set ‚Äì This is the attribute used for Semaphore bits. These bits are set by read in case the previous values

were 0b. In this case the read value is 0b; otherwise the read value is 1b. Cleared by a write of 0b.

R/W1 Read, Write-1 only register. Once a 1b has been written on a bit, the bit cannot be cleared to 0b.

Table 8-5. PHY Register Nomenclature

LH Latched High. Event is latched and erased when read.

Latched Low. Event is latched and erased when read. For example, Link Loss is latched when the PHY

Control Register bit 2 = 0b. After read, if the link is good, the PHY Control Register bit 2 is set to 1b.

RO Read Only.

R/W Read and Write.

SC Self-Clear. The bit is set, automatically executed, and then reset to normal operation.

CR Clear after Read. For example, 1000BASE-T Status Register bits 7:0 (Idle Error Counter).

Update Value written to the register bit does not take effect until software PHY reset is executed.

Table 8-4. I210 Register Field Attributes (Continued)

Attribute Description