Data Sheet

Programming Interface — Ethernet Controller I210
365
Reserved and/or undefined addresses: any register address not explicitly declared in this specification
should be considered to be reserved, and should not be written to. Writing to reserved or undefined
register addresses might cause indeterminate behavior. Reads from reserved or undefined
configuration register addresses might return indeterminate values unless read values are explicitly
stated for specific addresses.
Initial values: most registers define the initial hardware values prior to being programmed. In some
cases, hardware initial values are undefined and is listed as such via the text undefined, unknown, or X.
Such configuration values might need to be set via Flash configuration or via software in order for
proper operation to occur; this need is dependent on the function of the bit. Other registers might cite
a hardware default, which is overridden by a higher-precedence operation. Operations that might
supersede hardware defaults might include a valid Flash load, completion of a hardware operation
(such as hardware auto-negotiation), or writing of a different register whose value is then reflected in
another bit.
For registers that should be accessed as 32-bit double words, partial writes (less than a 32- bit double
word) do not take effect (the write is ignored). Partial reads returns all 32 bits of data regardless of
the byte enables.
Note: Partial reads to Read-on-Clear (ICR) registers can have unexpected results since all 32 bits
are actually read regardless of the byte enables. Partial reads should not be done.
All statistics registers are implemented as 32-bit registers. Though some logical statistics
registers represent counters in excess of 32 bits in width, registers must be accessed using
32-bit operations (for example, independent access to each 32-bit field). When reading 64
bits statistics registers, the least significant 32-bit register should be read first.
Refer to the special notes for VLAN Filter Table, Multicast Table Arrays and Packet Buffer Memory,
which appear in the specific register definitions.
The I210 register fields are assigned one of the attributes listed in Table 8-4.
Table 8-4. I210 Register Field Attributes
Attribute Description
RW Read-Write field: Register bits are read-write and can be either set or cleared by software to the desired state.
RWM
Read-Write Modified field: Register bits are read-write and can be either set or cleared by software to the desired
state. However, the value of this field might be modified by the hardware to reflect a status change.
RO
Read-only register: Register bits are read-only and should not be altered by software. Register bits might be
initialized by hardware mechanisms such as pin strapping, serial Flash or reflect a status of the hardware state.
ROM
Read-only Modified field: Register bits are read-only and will be either set or cleared by software upon read
operation. However, the value of this field might be modified by the hardware to reflect a status change.
R/W1C
Read-only status, Write-1-to-clear status register: Register bits indicate status when read, a set bit indicating a
status event can be cleared by writing a 1b. Writing a 0b to R/W1C bit has no effect.
Rsv Reserved. Write 0b to these fields and ignore read.
RC
Read-only status, Read-to-clear status register: Register bits indicate status when read, a set bit indicating a status
event is cleared by reading it.
SC
Self Clear field: a command field that is self clearing. These field are read as zero after the requested operation is
done.
WO Write only field: a command field that can not be read, These field read values are undefined.
RC/W
Read-Write status, Read-to-clear status register: Read-to-clear status register. Register bits indicate status when
read. Register bits are read-write and can be either set or cleared by software to the desired state.