Data Sheet

Programming Interface — Ethernet Controller I210
363
8.1.1.5.2 IODATA (I/O Offset 0x04)
The IODATA register must always be written as a Dword access when the IOADDR register contains a
value for the internal register and memories (for example, 0x00000-0x1FFFC). In this case, writes that
are less than 32 bits are ignored.
Reads to IODATA of any size returns a Dword of data. However, the chipset or CPU might only return a
subset of that Dword.
For software programmers, the IN and OUT instructions must be used to cause I/O cycles to be used on
the PCIe bus. Where 32-bit quantities are required on writes, the source register of the OUT instruction
must be EAX (the only 32-bit register supported by the OUT command).
Writes and reads to IODATA when the IOADDR register value is in an undefined range (0x20000-
0xFFFFFFFC) should not be performed. Results cannot be determined.
Notes: There are no special software timing requirements on accesses to IOADDR or IODATA. All
accesses are immediate, except when data is not readily available or acceptable. In this case,
the I210 delays the results through normal bus methods (for example, split transaction or
transaction retry).
Because a register/memory read or write takes two I/O cycles to complete, software must
provide a guarantee that the two I/O cycles occur as an atomic operation. Otherwise, results
can be non-deterministic from the software viewpoint.
Software should access CSRs via I/O address space or configuration address space but should
not use both mechanisms at the same time.
8.1.1.5.3 Undefined I/O Offsets
I/O offsets 0x08 through 0x1F are considered to be reserved offsets with the I/O window. Dword reads
from these addresses returns 0xFFFF; writes to these addresses are discarded.
8.1.1.6 Configuration Access to Internal Registers and Memories
To support legacy pre-boot 16-bit operating environments without requiring I/O address space, the
I210 enables accessing CSRs via configuration address space by mapping the IOADDR and IODATA
registers into configuration address space. The registers mapping in this case is listed in Table 8-3.
Note: To enable CSR access via configuration address space the CSR_conf_en Flash bit should be
set (see Section 6.2.15).
Software writes data to an internal CSR via configuration space in the following manner:
1. CSR address is written to the IOADDR register where:
a. Bit 31 (IOADDR.Configuration IO Access Enable) of the IOADDR register should be set to 1b.
Table 8-3. IOADDR and IODATA in Configuration Address Space
Configuration
Address
Abbreviation Name RW Size
0x98 IOADDR
Internal register or internal memory location address.
0x00000-0x1FFFF– Internal registers and memories.
0x20000-0x7FFFFF – Undefined.
RW 4 bytes
0x9C IODATA
Data field for reads or writes to the internal register or internal memory
location as identified by the current value in IOADDR. All 32 bits of this
register can be read or written to.
RW 4 bytes