Data Sheet

Ethernet Controller I210 — Programming Interface
362
8.1.1.3 Memory-Mapped Access to MSI-X Tables
The MSI-X tables can be accessed as direct memory-mapped offsets from the base address register
(BAR3; refer to Section 9.3.11). Refer to Section 8.1.3 for the appropriate offset for each specific
internal MSI-X register.
8.1.1.4 Memory-Mapped Access to Expansion ROM
The Expansion/Option ROM module located in the external Flash (refer to Section 3.3.9.1) can be
accessed as a memory-mapped Expansion ROM. Accesses to offsets starting from the Expansion ROM
Base address reference the Flash, provided that access is enabled through the LAN Boot Disable bit in
NVM Initialization Control 3 word, and if the Expansion ROM Base Address register contains a valid
(non-zero) base memory address.
8.1.1.5 I/O-Mapped Access to Internal Registers and Memories
To support pre-boot operation (prior to the allocation of physical memory base addresses), all internal
registers and memories can be accessed using I/O operations. I/O accesses are supported only if an I/
O Base Address is allocated and mapped (BAR2; refer to Section 9.3.11), the BAR contains a valid
(non-zero value), and I/O address decoding is enabled in the PCIe configuration.
When an I/O BAR is mapped, the I/O address range allocated opens a 32-byte window in the system I/
O address map. Within this window, two I/O addressable registers are implemented: IOADDR and
IODATA. The IOADDR register is used to specify a reference to an internal register or memory, and
then the IODATA register is used as a window to the register or memory address specified by IOADDR:
8.1.1.5.1 IOADDR (I/O Offset 0x00)
The IOADDR register must always be written as a Dword access. Writes that are less than 32 bits are
ignored. Reads of any size return a Dword of data; however, the chipset or CPU might only return a
subset of that Dword.
For software programmers, the IN and OUT instructions must be used to cause I/O cycles to be used on
the PCIe bus. Because writes must be to a 32-bit quantity, the source register of the OUT instruction
must be EAX (the only 32-bit register supported by the OUT command). For reads, the IN instruction
can have any size target register, but it is recommended that the 32-bit EAX register be used.
Because only a particular range is addressable, the upper bits of this register are hard coded to zero.
Bits 31 through 20 cannot be written to and are always read back as 0b.
At hardware reset (LAN_PWR_GOOD) or PCI reset, this register value resets to 0x00000000. Once
written, the value is retained until the next write or reset.
Table 8-2. IOADDR and IODATA in I/O Address Space
Offset Abbreviation Name RW Size
0x00 IOADDR
Internal register, internal memory, or Flash location address.
0x00000-0x1FFFF – Internal registers and memories.
0x20000-0xFFFFFFFF – Undefined.
RW 4 bytes
0x04 IODATA
Data field for reads or writes to the internal register, internal
memory, or Flash location as identified by the current value in
IOADDR. All 32 bits of this register can be read or written to.
RW 4 bytes
0x08 – 0x1F Reserved Reserved. RO 4 bytes