Data Sheet

Programming Interface — Ethernet Controller I210

361

8.0 Programming Interface

8.1 Introduction

This section details the programmer visible state inside the I210. In some cases, it describes hardware

structures invisible to software in order to clarify a concept. The I210's address space is mapped into

four regions with PCI Base Address registers described in Section 9.3.11. These regions are listed in

Table 8-1.

The internal register/memory space is described in the following sections. The PHY registers are

accessed through the MDIO interface.

8.1.1 Memory, I/O Address and Configuration Decoding

8.1.1.1 Memory-Mapped Access to Internal Registers and Memories

The internal registers and memories might be accessed as direct memory-mapped offsets from the

base address register (BAR0 or BAR 0/1; refer to Section 9.3.11). Refer to Section 8.1.3 for the

appropriate offset for each specific internal register.

8.1.1.2 Memory-Mapped Access to Flash

The external Flash can be accessed using direct memory-mapped offsets from the Memory Base

Address register (BAR0 in 32-bit addressing or BAR0/BAR1 in 64-bit addressing; refer to

Section 9.3.11). For accesses, the offset from the Memory BAR minus 128 KB corresponds to the

physical address within the external Flash device. Memory mapped accesses to the external Flash

device are enabled when the value of the FLBAR_Size field in the Flash (refer to Section 6.2.25) is not

000b.

Table 8-1. Address Space Regions

Addressable Content How Mapped Size of Region

Internal registers, memories and Flash (Memory BAR) Direct memory-mapped 128 KB + Flash Size

1. The Flash space in the Memory CSR and Expansion ROM Base Address are mapped to different Flash memory regions. Accesses

to the Memory BAR at offset 128 KB are mapped to the Flash device at offset 0x0, while accesses to the Expansion ROM at offset

0x0 are mapped to the fixed Flash region that starts at NVM word address 0x001000. See Section 3.3.3.1. The Expansion ROM

region has a fixed provisioned size of 512 KB.

Flash (optional) Direct memory-mapped 64 KB to 8 MB

Expansion ROM (optional) Direct memory-mapped 512 KB

Internal registers and memories, Flash (optional) I/O window mapped 32 bytes

2. The internal registers and memories can be accessed though I/O space indirectly as explained in the sections that follow.

MSI-X (optional) Direct memory-mapped 16 KB