Data Sheet

Ethernet Controller I210 —Inline Functions

352

2. The selected AUTT0 or AUTT1 flags are set in the TSICR register. If the AUTT interrupt is enabled by

the TSIM register and the 1588 interrupts are enabled by the Time_Sync flag in the ICR register

then an interrupt is asserted as well.

After the hardware reports that an event time was latched, the software should read the latched time in

the selected AUXSTMP registers. Software should read first the Low register and only then the High

7.8.4 Time SYNC Interrupts

Time Sync related interrupts can be generated by programming the TSICR and TSIM registers. The

TSICR register logs the interrupt cause and the TSIM register enables masking specific TSICR bits.

Detailed description of the Time Sync interrupt registers can be found in Section 8.16. Occurrence of a

Time Sync interrupt sets the ICR.Time_Sync interrupt bit.

7.8.5 PTP Packet Structure

The time sync implementation supports both the 1588 V1 and V2 PTP frame formats. The V1 structure

can come only as UDP payload over IPv4 while the V2 can come over L2 with its Ethertype or as a UDP

payload over IPv4 or IPv6. The 802.1AS uses only the layer 2 V2 format. The PTP frame formats over

L2 and over UDP are listed in the Table 7-64 and Table 7-65. The PTP V1 and V2 message formats are

listed in the Table 7-66 followed by SYNC packet format in Table 7-67. Table 7-68 and Table 7-69 list

the relevant fields that identify the PTP message that are the Control field for V1 message and the

MessageType field for V2 message. Then, Table 7-70 lists the device settings required to identify the

PTP packets.

Table 7-64. PTP Message Over Layer 2

Ethernet (L2) VLAN (Optional) PTP Ethertype PTP message

Table 7-65. PTP Message Over Layer 4

Ethernet (L2) IP (L3) UDP PTP message

Table 7-66. V1 and V2 PTP Message Header

Offset in Bytes V1 Fields V2 Fields

Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

versionPTP

transport Specific

messageType

1ReservedversionPTP

version Network message Length