Data Sheet

Ethernet Controller I210 —Inline Functions
350
— Tdelay is the transmission delay from the slave to the master. It can be calculated using T1...T4
as follow: Tdelay = [(T2-T1) + (T4-T3)] / 2
— The factor is a parameter that affects the speed of convergence. For a clock frequency of 125
MHz, an optimized factor equals 8. Table 7-65 lists the expected convergence time for some
cases while Tcycle equals 1 second and the slave-to-master clock frequency difference equals
100 ppm.
7.8.3.3 Target Time
The two target time registers TRGTTIML/H0 and TRGTTIML/H1 enable generating a time triggered
event to external hardware using one of the SDP pins according to the setup defined in the TSSDP and
TSAUXC registers (See Section 8.15.13 and Section 8.15.25). Each target time register is structured
the same as the SYSTIML/H registers. If the value of SYSTIML/H is equal or larger than the value of the
TRGTTIML/H registers, a change in level or a pulse is generated on the matched SDP outputs.
7.8.3.3.1 SYSTIM Synchronized Level Change Generation on SDP Pins
To generate a level change on one of the SDP pins when System Time (SYSTIM) reaches a pre-defined
value, the driver should do the following:
1. Select a specific SDP pin by setting the TSSDP.TS_SDPx_EN flag to 1b(while ‘x’ is 0, 1, 2 or 3).
2. Assign a target time register to the selected SDP by setting the TSSDP.TS_SDPx_SEL field to 00b or
01b if level change should occur based on TRGTTIML/H0 or TRGTTIML/H1, respectively.
3. Define the selected SDPx pin as output, by setting the appropriate SDPx_IODIR bit (while ‘x’ is 0, 1,
2, or 3) in the CTRL or CTRL_EXT registers.
4. Program the target time TRGTTIML/Hx (while ‘x’ is 0b or 1b) to the required event time.
5. Program the TRGTTIML/Hx to “Level Change” mode by setting the TSAUXC.PLSG bit to 0b and
TSAUXC.EN_TTx bit to 1b (while ‘x’ is 0b or 1b).
6. When the SYSTIML/H registers becomes equal or larger than the selected TRGTTIML/H registers,
the selected SDP changes its output level.
7.8.3.3.2 SYSTIM Synchronized Pulse Generation on SDP Pins
An output pulse can be generated by using one of the target time registers to define the beginning of
the pulse and the other target time registers to define the pulse completion time. To generate a pulse
on one of the SDP pins when System Time (SYSTIM) reaches a pre-defined value, the driver should do
the following:
1. Select a specific SDP pin by setting the TSSDP.TS_SDPx_EN flag to 1b (while ‘x’ is 0, 1, 2 or 3).
2. Select the target time register for the selected SDP that defines the beginning of the output pulse.
It is done by setting the TSSDP.TS_SDPx_SEL field to 00b or 01b if level change should occur when
SYSTIML/H equals TRGTTIML/H0 or TRGTTIML/H1, respectively.
3. Define the selected SDPx pin as output, by setting the appropriate SDPx_IODIR bit (while ‘x’ is 0, 1,
2, or 3) in the CTRL or CTRL_EXT registers.
4. Program the target time TRGTTIML/Hx (while ‘x’ is 0b or 1b) to the required event time. The
registers indicated by the TSSDP.TS_SDPx_SEL
define the leading edge of the pulse and the other
ones define the trailing edge of the pulse.
5. Program the TRGTTIML/Hx defined by the TSSDP.TS_SDPx_SEL to “Start of Pulse” mode by setting
the TSAUXC.PLSG bit to 1b and TSAUXC.EN_TTx bit to 1b (while ‘x’ is 0b or 1b). The other
TRGTTIML/Hx register should be set to Level Change mode by setting the TSAUXC.PLSG bit to 0b
and TSAUXC.EN_TTx bit to 1b (while ‘x’ is 0b or 1b).