Data Sheet

Inline Functions—Ethernet Controller I210
347
7.8.2.3 TimeSync Indications in Receive and Transmit Packet Descriptors
Certain indications are transferred between software and hardware regarding PTP packets. These
indications are enabled when the Disable systime bit in the TSAUXC register is cleared. Further more,
transmit timestamping is enabled by the TSYNCTXCTL.EN flag. Received packets for captured time are
identified according to the TSYNCRXCTL.Type and CTRLT and MSGT fields in the TSYNCRXCFG register.
2-step SYNC and Delay_Req packet transmission: The software sets the 2STEP_1588 bit in the
Advanced Transmit Data Descriptor. The hardware samples the transmission time in the TXSTMP
register. The software reads it for every packet and used the transmission time as required.
1-step SYNC packet transmission: On the transmit path the software sets the 1STEP_1588 bit in
the Advanced Transmit Data Descriptor. It should also set previously the 1588_Offset field in the
TSYNCTXCTL register. The hardware samples the transmission time and inserts it in the transmitted
packet at the offset defined by the 1588_Offset field. The software should prepare the space in the
transmitted packet by filling it with zero’s while the hardware replaces these zero’s by the transmission
timestamp. The transmission time stamp is an 80-bit field while the 32 LS bits specify the transmission
time in nsec units and the upper 48 bits specify the time in second units. Note that the 1588 timer in
the I210 contains only 32 bits that specify the second units. The additional upper 16 bits are taken from
the static SYSTIMTM register which is set by software (expected to be zero at all times). Timestamp
transmission on the wire is as follows: The MS byte of the SYSTIMTM register is transmitted first while
the LS byte of the nsec units is transmitted last (as shown in Table 7-67).
Packet reception: PTP packet identification is described in Section 7.8.5. L2 packets that are
identified by the EtherType are indicated by the “packet type” field in the receive descriptor. Those
packets that the hardware samples its reception time are also indicated by the TS or TSIP flags in the
advanced receive descriptors. Selecting between TS or TSIP reporting is controlled by the Timestamp
flag in the SRRCTL[n] register (per receive queue). If the TS flag is set, the packet reception time is
sampled by the hardware in the RXSTMPL/H registers. These registers are locked until the software
reads its value. If the TSIP flag is set, the packet reception time is posted to the packet buffer in host
memory as shown in Section 7.1.6.
7.8.3 Hardware Time Sync Elements
All time sync hardware is initialized as defined in the registers section upon MAC reset. The time sync
logic is enabled if the TSAUXC.Disable systime flag is cleared.
The 1588 logic includes multiple registers larger than 32 bits which are indicated as xxxL (Low portion -
LS) and xxxH (High portion - MS). When software accesses these registers (either read or write) it
should access first the xxxL register (LS) and only then the xxxH register (MS). Accessing the xxxH
might impact the hardware functionality which should be triggered only after both portions of the
register are valid.
7.8.3.1 Capture Timestamp Mechanism
The timestamp logic is located on transmit and receive paths as close as possible to the PHY interface.
The timestamp is captured at the beginning of the packet as shown in the Figure 7-21. These rules
keep the latency between the captured timestamp and transmission time as deterministic as possible.
The 1588 logic is functional at all link speeds; however, the latency parameters characterized at this
time is only for 100 Mb/s. The measured latency parameters in a stand-alone setup are listed in
Table 7-62. When measured against a commercial link partner using an arithmetic mean and
exponential smoothing, a shift of approximately 40 ns is used as listed in Table 7-63.