Data Sheet

Ethernet Controller I210 —Inline Functions
346
• The slave software responds back by sending the Delay_Req packet (for those SYNC packets that
the slave “wish” to respond). The Delay_Req packet is indicated to the hardware by setting the
2STEP_1588 flag in the Advanced Transmit Data Descriptor. The transmission time is extracted
from the TXSTMP register the same as the master processes the transmitted SYNC packets.
• The Master receives the Delay_Req packet and its reception time is posted to the “timestamp
bytes” in the packet buffer in host memory.
• The master software sends back the received timestamp to the slave which has all required
timestamps.
• The slave adjust its time according to the following equation (or a low-pass version of the
equation):
Slave Adjust Time = - [(T2-T1) - (T4-T3)] / 2
While using the following notations:
- T1: Sync packet transmission time in the master (based on master clock)
- T2: Sync packet reception time in the slave (based on slave clock)
- T3: Delay_Request transmission time in the slave (based on slave clock)
- T4: Delay_Request reception time in the master (based on master clock)
7.8.2.2.4 1-step Time Synchronization Phase Procedure
Packet processing in the master and the Slave for 1-step procedure is almost identical to the 2-step
procedure as follow:
• The master software sends the SYNC packet while indicating it to the hardware by the 1STEP_1588
flag. Doing so, the hardware inserts the transmission time in the SYNC packet.
• The slave samples the reception time of the SYNC and extract its transmission time at the master.
• From this point the flow is identical to the 2-step procedure.
Figure 7-20. Sync Flow and Offset Calculation
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Master Slave
T1
T2
T3
T4
T0 + delta TT0
Master to Slave
Transmission delay
Slave to Master
Transmission delay
T1, T2, T3 and T4
are sampled by the HW
Calculated delta T = [(T2-T1)-(T4-T3)]/2