Data Sheet

Inline Functions—Ethernet Controller I210
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transmission time at the master and its reception time at the slave. The slave calculates the time gap
between consecutive SYNC packets defined by the master clock. It then calibrates itself to get the same
time gap defined by its own clock. During this phase the slave also sets its time to be as close as
possible to the master time (as accurate as the transmission delay and software latencies).
In order to minimize sampling inaccuracy, both master and slave sample the packets transmission and
reception time at a location in the hardware that has as much as possible deterministic delay from the
PHY interface.
Packet processing in the master and the Slave
• The master software indicates the SYNC packet to the hardware by setting the 2STEP_1588 flag in
the Advanced Transmit Data Descriptor. Setting this flag, the hardware samples its transmission
time by the TXSTMP register. The software reads its value and sends the transmission time in a
Follow_Up packet.
• The SYNC packet is received by the slave and its reception time is posted to the “timestamp bytes”
in the packet buffer in host memory. The Follow_Up packet is also received and posted to the
software processing. The software uses these parameters to calculate the time gap between
consecutive packets by its own clock compared to the master clock taking the required corrective
action.
7.8.2.2.2 1-step Clocks Calibration Procedure
The I210 supports the 1-step procedure. In 1-step procedure, the hardware inserts the transmission
time to the sent SYNC packets at the master (as follows). All the rest is the same as the 2-step
procedure described above.
• The software indicates the SYNC packets to the hardware by setting the 1STEP_1588 flag in the
Advanced Transmit Data Descriptor. Setting this flag, the hardware does the following:
— Samples the packet transmission time
— Auto-inserts the packet transmission timestamp at the offset defined by the 1588_Offset field
in the TSYNCTXCTL register
— Insert the Ethernet CRC while including the timestamp in the CRC calculation
— The UDP checksum is not updated by the inserted timestamp. It means that 1-step is limited
for PTP over L2 or PTP over UDP/IPv4 while the UDP checksum is not used (equals to zero).
7.8.2.2.3 2-step Time Synchronization Phase Procedure
The complete synchronization scheme is shown in Figure 7-20. It relies on measured timestamp of
Sync packets transmission and reception by the master and the slave. The scheme is based on the
following two basic assumptions:
• The clocks at both nodes are almost identical (achieved in the first step)
• Transmission delays between the master to the slave and backward are symmetric
The master’s software sends periodically Sync packets to each slave followed by the Follow_Up packet
(as explained in the Clocks Calibration (2-step procedure). The responds back by sending Delay_Req
packets which are sampled by the slave and the master. The master provides back its parameters
which are used by the slave to calibrate its time. Following are the detailed software hardware steps.
Packet processing in the master and the slave
• The master software sends the SYNC packet and Follow_Up packet as described in the Clocks
Calibration (2-step procedure) procedure.
• Processing these packets by the slave is also the same as the Clocks Calibration (2-step procedure)
procedure