Data Sheet

Ethernet Controller I210 —Interconnects

PCIe's physical layer consists of a differential transmit pair and a differential receive pair. Full-duplex

data on these two point-to-point connections is self-c such that no dedicated clock signals are required.

The bandwidth of this interface increases linearly with frequency.

The packet is the fundamental unit of information exchange and the protocol includes a message space

to replace the various side-band signals found on many buses today. This movement of hard-wired

signals from the physical layer to messages within the transaction layer enables easy and linear

physical layer width expansion for increased bandwidth.

The common base protocol uses split transactions and several mechanisms are included to eliminate

wait states and to optimize the reordering of transactions to further improve system performance.

3.1.1.1 Architecture, Transaction and Link Layer Properties

• Split transaction, packet-based protocol

• Common flat address space for load/store access (such as PCI addressing model)

— Memory address space of 32-bits to allow compact packet header (must be used to access

addresses below 4 GB)

— Memory address space of 64-bit using extended packet header

• Transaction layer mechanisms:

— PCI-X style relaxed ordering

— Optimizations for no-snoop transactions

• Credit-based flow control

• Packet sizes/formats:

— Maximum upstream (write) payload size of 512 bytes

— Maximum downstream (read) payload size of 512 bytes

• Reset/initialization:

— Frequency/width/profile negotiation performed by hardware

• Data integrity support

— Using CRC-32 for transaction layer packets

• Link layer retry for recovery following error detection

— Using CRC-16 for link layer messages

• No retry following error detection

— 8b/10b encoding with running disparity

• Software configuration mechanism:

— Uses PCI configuration and bus enumeration model

— PCIe-specific configuration registers mapped via PCI extended capability mechanism

• Baseline messaging:

— In-band messaging of formerly side-band legacy signals (such as interrupts, etc.)

— System-level power management supported via messages

• Power management:

— Full support for PCI-PM

— Wake capability from D3cold state

— Compliant with ACPI, PCI-PM software model