Data Sheet

Inline Functions—Ethernet Controller I210
341
As shown in Figure 7-18, DCA provides a mechanism where the posted write data from an I/O device,
such as an Ethernet NIC, can be placed into CPU cache with a hardware pre-fetch. This mechanism is
initialized upon a power good reset. A software device driver for the I/O device configures the I/O
device for DCA and sets up the appropriate DCA target ID for the device to send data. The device then
encapsulates that information in PCIe TLP headers, in the TAG field, to trigger a hardware pre-fetch by
the MCH /IOH to the CPU cache.
DCA implementation is controlled by separated registers (RXCTL and TXCTL) for each receive and
transmit queue. In addition, a DCA Enable bit can be found in the DCA_CTRL register, and a DCA_ID
register, in order to make visible the function, device, and bus numbers to the driver.
The RXCTL and TXCTL registers can be written by software on the fly and can be changed at any time.
When software changes the register contents, hardware applies changes only after all the previous
packets in progress for DCA have been completed.
However, in order to implement DCA, the I210 has to be aware of the Crystal Beach version used.
Software driver must initialize the I210 to be aware of the Crystal Beach version. A register named
DCA_CTRL is used in order to properly define the system configuration.
There are 2 modes for DCA implementation:
1. Legacy DCA: The DCA target ID is derived from CPU ID.
2. DCA: The DCA target ID is derived from APIC ID.
The software driver selects one of these modes through the DCA_mode register.
The details of both modes are described in the following sections.
7.7.1.2 Details of Implementation
7.7.1.2.1 PCIe Message Format for DCA