Data Sheet

Inline Functions—Ethernet Controller I210
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The I210 reports parity errors in the PEIND register according to the region in which the parity error
occurred (PCIe, DMA, LAN Port or Management). An interrupt is issued via the ICR.FER bit on
occurrence of a parity error. Parity error interrupt generation per region can be masked via the PEINDM
register.
Additional per region granularity in parity or ECC enablement and reporting of parity error or ECC parity
correction occurrence is supported in the following registers:
1. PCIe region:
a. The PCIEERRCTL and PCIEECCCTL registers enable parity checks and ECC parity correction
respectively in the various rams in the PCIe region.
b. The PCIEERRSTS and PCIEECCSTS registers report parity error and ECC parity correction
occurrence in the various rams in the PCIe region. Only parity errors that were not corrected by
the ECC circuitry are reported by asserting the PEIND.pcie_parity_fatal_ind bit and the ICR.FER
bit. Parity errors that were corrected by the internal ECC circuit do not generate an interrupt but
are logged in the PCIEECCSTS register.
2. DMA region:
a. The PBECCSTS register enables ECC parity correction in the various rams in the DMA region.
b. The PBECCSTS register reports occurrence of ECC parity correction events in the various rams
in the DMA region. Only parity errors that were not corrected are reported by setting the
PEIND.dma_parity_fatal_ind bit and the ICR.FER bit. Parity errors that were corrected by the
internal ECC circuitry don’t generate an interrupt but are logged in the PBECCSTS register.
3. LAN Port region:
a. The LANPERRCTL register enables parity checks in the various rams in the LAN Port region.
b. The LANPERRSTS register reports detection of parity errors. The parity errors that were not
corrected are reported via the PEIND.lanport_parity_fatal_ind bit and the ICR.FER bit.
Notes:
1. An interrupt to the Host is generated on occurrence of a fatal memory error if the appropriate mask
bits in the PEINDM register are set and the IMS.FER Mask bit is set.
2. All Parity error checking can be disabled via the GPAR_EN bit in the Initialization Control Word 1
Flash word (See Section 6.2.2) or by clearing the PCIEERRCTL.GPAR_EN bit (See Section 8.24.4).
7.6.1 Software Recovery From Parity Error Event
If a parity error was detected in one of the internal control memories of the DMA, PCIe or LAN port
clusters, the consistency of the receive/transmit flow can not be guaranteed any more. In this case the
traffic on the PCIe interface is stopped, since this is considered a fatal error.
To recover from a parity error event software should initiate the following actions depending on the
region in which the parity error occurred.
7.6.1.1 Recovery from PCIe Parity Error Event
To recover from a parity error condition in the PCIe region, the software device driver should:
1. Issue a Device Reset by asserting the CTRL.RST bit.
2. wait at least 3 milliseconds after setting CTRL.RST bit before attempting to check if the bit was
cleared or before attempting to access any other register.
3. Initiate the master disable algorithm as defined in Section 5.2.3.3.
4. Clear the PCIe parity error status bits that were set in the PCIEERRSTS register.