Data Sheet

Inline Functions—Ethernet Controller I210
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• If the regular VLAN is inserted using the switch based VLAN insertion mechanism or from
the descriptor (see Section 7.4.3.1), and the packet does not contain an external VLAN,
the packet is dropped, and if configured, the queue from which the packet was sent is
disabled.
7.4.5.2 Receive Behavior With External VLAN
When the I210 is working in this mode, it assumes that all packets received have at least one VLAN,
including a packet received or sent on the manageability interface.
One exception to this rule are flow control PAUSE packets which are not expected to have any VLAN.
Other packets might contain no VLAN, however a received packet that does not contain the first VLAN
is forwarded to the host but filtering and offloads are not applied to this packet.
See Table 7-57 for the supported receive processing functions when the device is set to “Double VLAN”
mode.
Stripping of VLAN is done on the second VLAN if it exists. All the filtering functions of the I210 ignore
the first VLAN in this mode.
The presence of a first VLAN tag is indicated it in the RDESC.STATUS.VEXT bit.
Queue assignment of the Rx packets is not affected by the external VLAN header. It might depend on
the internal VLAN, MAC address or any upper layer content as described in Section 7.1.1.
7.5 Configurable LED Outputs
The I210 implements 3 output drivers intended for driving external LED circuits. Each of the 3 LED
outputs can be individually configured to select the particular event, state, or activity, which is
indicated on that output. In addition, each LED can be individually configured for output polarity as well
as for blinking versus non-blinking (steady-state) indication.
The configuration for LED outputs is specified via the LEDCTL register. Furthermore, the hardware-
default configuration for all the LED outputs, can be specified via Flash fields, thereby supporting LED
displays configurable to a particular OEM preference.
Each of the 3 LED's might be configured to use one of a variety of sources for output indication. The
MODE bits control the LED source as described in Table 7-58.
The IVRT bits allow the LED source to be inverted before being output or observed by the blink-control
logic. LED outputs are assumed to normally be connected to the negative side (cathode) of an external
LED.
Table 7-57. Receive Processing in Double VLAN Mode
VLAN Headers Status.VEXT Status.VP Packet Parsing Rx Offload Functions
External and internal 1 1 + +
Internal Only Not supported
V-Ext 1 0 + +
None
1
1. A few examples for packets that might not carry any VLAN header might be: Flow control and Priority Flow Control; LACP; LLDP;
GMRP; 802.1x packets
0 0 + (flow control only) -