Data Sheet

Ethernet Controller I210 —Inline Functions
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• There are 8 flex filters. The content of each filter is described in Section 7.1.2.5. The immediate
interrupt action of each filter can be enabled or disabled. If one of the filters detects an adequate
packet, an immediate interrupt is issued.
• When VLAN priority filtering is enabled, VLAN packets must trigger an immediate interrupt when
the VLAN Priority is equal to or above the VLAN priority threshold. This is regardless of the status of
the 2-tuple or Flex filters.
• The SYN packets filter defined in Section 7.1.2.6 and the ethernet type filters defined in section
Section 7.1.2.3 might also be used to indicate low latency interrupt conditions.
Note: Immediate interrupts are available only when using advanced receive descriptors and not for
legacy descriptors.
Note: Packets that are dropped or have errors do not cause a Low Latency Interrupt.
7.3.6.1 Rate Control Mechanism
In a network with lots of latency sensitive traffics the Low Latency Interrupt can eliminate the Interrupt
throttling capability by flooding the Host with too many interrupts (more than the Host can handle).
In order to mitigate the above, the I210 supports a credit base mechanism to control the rate of the
Low Latency Interrupts.
Rules:
• The default value of each counter is 0b (no moderation). This also preserves backward
compatibility.
• The counter increments at a configurable rate, and saturates at the maximum value (31d).
— The configurable rate granularity is 4 s (250K interrupt/sec. down to 250K/32 ~ 8K interrupts
per sec.).
• A LLI might be issued as long as the counter value is strictly positive (> zero).
— The credit counter allows bursts of low latency interrupts but the interrupt average are not
more than the configured rate.
• Each time a Low Latency Interrupt is fired the credit counter decrements by one.
• Once the counter reaches zero, a low latency interrupt cannot be fired
— Must wait for the next ITR expired or for the next incrementing of this counter (if the EITR
expired happened first the counter does not decrement).
The EITR and GPIE registers manage rate control of LLI:
•The LL Interval field in the GPIE register controls the rate of credits
•The 5-bit LL Counter field in the EITR register contains the credits
7.3.7 TCP Timer Interrupt
7.3.7.1 Introduction
The TCP Timer interrupt provides an accurate and efficient way for a periodic timer to be implemented
using hardware. The driver would program a timeout value (usual value of 10 ms), and each time the
timer expires, hardware sets a specific bit in the EICR. When an interrupt occurs (due to normal
interrupt moderation schemes), software reads the EICR and discovers that it needs to process timer
events during that DPC.