Data Sheet

Ethernet Controller I210 —Inline Functions
328
7.3.4.1 Auto-Clear
In systems that support MSI-X, the interrupt vector allows the interrupt service routine to know the
interrupt cause without reading the EICR. With interrupt moderation active, software load from
spurious interrupts is minimized. In this case, the software overhead of a I/O read or write can be
avoided by setting appropriate EICR bits to auto-clear mode by setting the corresponding bits in the
Extended Interrupt Auto-clear Enable Register (EIAC).
When auto-clear is enabled for an interrupt cause, the EICR bit is set when a cause event mapped to
this vector occurs. When the EITR Counter reaches zero, the MSI-X message is sent on PCIe. Then the
EICR bit is cleared and enabled to be set by a new cause event. The vector in the MSI-X message
signals software the cause of the interrupt to be serviced.
It is possible that in the time after the EICR bit is cleared and the interrupt service routine services the
cause, for example checking the transmit and receive queues, that another cause event occurs that is
then serviced by this ISR call, yet the EICR bit remains set. This results in a “spurious interrupt”.
Software can detect this case, for example if there are no entries that require service in the transmit
and receive queues, and exit knowing that the interrupt has been automatically cleared. The use of
interrupt moderations through the EITR register limits the extra software overhead that can be caused
by these spurious interrupts.
7.3.4.2 Write to Clear
In the case where the driver wishes to configure itself in MSI-X mode to not use the “auto-clear”
feature, it might clear the EICR bits by writing to the EICR register. Any bits written with a 1b is
cleared. Any bits written with a 0b remain unchanged.
7.3.4.3 Read to Clear
The EICR and ICR registers are cleared on a read.
Note: The driver should never do a read-to-clear of the EICR when in MSI-X mode, since this might
clear interrupt cause events which are processed by a different interrupt handler (assuming
multiple vectors).
7.3.5 Interrupt Moderation
An interrupt is generated upon receiving of incoming packets, as throttled by the EITR registers (see
Section 8.8.14). There is an EITR register per MSI-X vector.
In MSI-X mode, each active bit in EICR can trigger the interrupt vector it is allocated to. Following the
allocation, the EITR corresponding to the MSI-X vector is tied to one or more bits in EICR.
When multi vector MSI-X is not activated, the interrupt moderation is controlled by register EITR[0].
Software can use EITR to limit the rate of delivery of interrupts to the host CPU. This register provides
a guaranteed inter-interrupt delay between interrupts asserted by the network controller, regardless of
network traffic conditions.
The following formula converts the inter-interrupt interval value to the common 'interrupts/sec.'
performance metric:
interrupts/sec = (1 * 10
-6
sec x interval)
-1