Data Sheet

Inline Functions—Ethernet Controller I210
327
7.3.3.10 Extended Interrupt Auto Mask Enable Register (EIAM)
Each bit set in this register enables clearing of the corresponding bit in the extended mask register
following read or write-to-clear to EICR. It also enables setting of the corresponding bit in the extended
mask register following a write-to-set to EICS.
This mode is provided in case MSI-X is not used, and therefore auto-clear through EIAC register is not
available.
In MSI-X mode, the driver software might set the bits of this register to select mask bits that must be
reset during interrupt processing. In this mode, each bit in this register enables clearing of the
corresponding bit in EIMC following interrupt generation.
7.3.3.11 GPIE Register
There are a few bits in the GPIE register that define the behavior of the interrupt mechanism. The
setting of these bits is different in each mode of operation. Table 7-52lists the recommended setting of
these bits in the different modes:
7.3.4 Clearing Interrupt Causes
The I210 has three methods available to clear EICR bits: Auto-clear, clear-on-write, and clear-on-read.
ICR bits might only be cleared with clear-on-write or clear-on-read.
Table 7-52. Settings for Different Interrupt Modes
Field Bit(s)
Initial
Value
Description
INT-x/
MSI +
Legacy
INT-x/
MSI +
Extend
MSI-X
Multi
Vector
MSI-X
Single
Vector
NSICR 0 0b
Non Selective Interrupt clear on read: When set,
every read of the ICR register clears the ICR
register. When this bit is cleared, an ICR register
read causes the ICR register to be cleared only if
an actual interrupt was asserted or IMS = 0x0.
0b
1
1. In systems where interrupt sharing is not expected, the NSICR bit can be set by legacy drivers also.
As this register affects the way the hardware interprets write operations to other interrupt control
registers, it should be set to the correct mode before accessing other interrupt control registers.
1b 1b 1b
Multiple_
MSIX
40b
Multiple_MSI-X - multiple vectors:
0b = non-MSI-X or MSI-X with 1 vector IVAR
maps Rx/Tx causes to 4 EICR bits, but MSIX[0]
is asserted for all.
1b = MSIX mode, IVAR maps Rx/Tx causes to 5
EICR bits.
When set, the EICR register is not clear on read.
0b 0b 1b 0b
EIAME 30 0b
EIAME: When set, upon firing of an MSI-X
message, mask bits set in EIAM associated with
this message are cleared. Otherwise, EIAM is
used only upon read or write of EICR/EICS
registers.
0b 0b 1b 1b
PBA_
support
31 0b
PBA support: When set, setting one of the
extended interrupts masks via EIMS causes the
PBA bit of the associated MSI-X vector to be
cleared. Otherwise, the I210 behaves in a way
that supports legacy INT-x interrupts.
Should be cleared when working in INT-x or MSI
mode and set in MSI-X mode.
0b 0b 1b 1b