Data Sheet

Ethernet Controller I210 —Inline Functions
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The interrupt causes include:
1. The Receive and Transmit queues — Each queue (either Tx or Rx) can be mapped to one of the 4
interrupt causes bits (RxTxQ) available in this register according to the mapping in the IVAR
registers
2. Indication for the TCP timer interrupt.
3. Legacy and other indications — When any interrupt in the Interrupt Cause register is active.
Writing a 1b clears the corresponding bit in this register. Reading this register auto-clears all bits.
7.3.3.6.2 MSI-X Mode (GPIE.Multiple_MSIX = 1b)
This register records the interrupt vectors currently emitted. In this mode only the first 5 bits are valid.
For all the subsequent registers, in MSI-X mode, each bit controls the behavior of one vector.
Bits in this register can be configured to auto-clear when the MSI-X interrupt message is sent, in order
to minimize driver overhead when using MSI-X interrupt signaling.
Writing a 1b clears the corresponding bit in this register. Reading this register does not clear any bits.
7.3.3.7 Extended Interrupt Cause Set Register (EICS)
This register enables the software device driver to set EICR bits. Writing a 1b in a EICS bit causes the
corresponding bit in the EICR register to be set. Used usually to re-arm interrupts that the software
didn't have time to handle in the current interrupt routine.
7.3.3.8 Extended Interrupt Mask Set and Read Register (EIMS) & Extended
Interrupt Mask Clear Register (EIMC)
Interrupts appear on PCIe only if the interrupt cause bit is a one and the corresponding interrupt mask
bit is a one. Software blocks assertion of an interrupt by clearing the corresponding bit in the mask
register. The cause bit stores the interrupt event regardless of the state of the mask bit. Different Clear
(EIMC) and set (EIMS) registers make this register more “thread safe” by avoiding a read-modify-write
operation on the mask register. The mask bit is set for each bit written as a one in the set register
(EIMS) and cleared for each bit written as a one in the clear register (EIMC). Reading the set register
(EIMS) returns the current mask register value.
7.3.3.9 Extended Interrupt Auto Clear Enable Register (EIAC)
Each bit in this register enables clearing of the corresponding bit in EICR following interrupt generation.
When a bit is set, the corresponding bit in the EICR register is automatically cleared following an
interrupt. This feature should only be used in MSI-X mode.
When used in conjunction with MSI-X interrupt vector, this feature allows interrupt cause recognition,
and selective interrupt cause, without requiring software to read or write the EICR register; therefore,
the penalty related to a PCIe read or write transaction is avoided.
See section 7.3.4 for additional information on the interrupt cause reset process.