Data Sheet

Inline Functions—Ethernet Controller I210
325
7.3.3.1.2 Advanced Mode
In advanced mode, this register captures the interrupt causes not directly captured by the EICR. These
are infrequent management interrupts and error conditions.
Note that when EICR is used in advanced mode, the Rx /Tx related bits in ICR should be masked.
ICR bits are cleared on register read. If GPIE.NSICR = 0b, then the clear on read occurs only if no bit is
set in the IMS register or at least one bit is set in the IMS register and there is a true interrupt as
reflected in the ICR.INTA bit.
7.3.3.2 Interrupt Cause Set Register (ICS)
This register allows software to set bits in the ICR register. Writing a 1b in an ICS bit causes the
corresponding bit in the ICR register to be set. Used usually to re-arm interrupts the software device
driver didn't have time to handle in the current interrupt routine.
7.3.3.3 Interrupt Mask Set/Read Register (IMS)
An interrupt is enabled if its corresponding mask bit in this register is set to 1b, and disabled if its
corresponding mask bit is set to 0b. A PCIe interrupt is generated whenever one of the bits in this
register is set, and the corresponding interrupt condition occurs. The occurrence of an interrupt
condition is reflected by having a bit set in the Interrupt Cause Register (ICR).
Reading this register returns which bits have an interrupt mask set.
A particular interrupt might be enabled by writing a 1b to the corresponding mask bit in this register.
Any bits written with a 0b are unchanged. Thus, if software desires to disable a particular interrupt
condition that had been previously enabled, it must write to the Interrupt Mask Clear (IMC) Register,
rather than writing a 0b to a bit in this register.
7.3.3.4 Interrupt Mask Clear Register (IMC)
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished by writing a 1b
to the corresponding bit in this register. Bits written with 0b are unchanged (their mask status does not
change).
7.3.3.5 Interrupt Acknowledge Auto-mask register (IAM)
An ICR read or write has the side effect of writing the contents of this register to the IMC register to
auto-mask additional interrupts from the ICR bits in the locations where the IAM bits are set. If
GPIE.NSICR = 0b, then the copy of this register to the IMC register occurs only if at least one bit is set
in the IMS register and there is a true interrupt as reflected in the ICR.INTA bit.
7.3.3.6 Extended Interrupt Cause Registers (EICR)
7.3.3.6.1 MSI/INT-A Mode (GPIE.Multiple_MSIX = 0b)
This register records the interrupts causes, to provide Software with information on the interrupt
source.