Data Sheet

Ethernet Controller I210 —Inline Functions
324
7.3.3 Legacy Interrupt Registers
The interrupt logic consists of the registers listed in Table 7-50 and Table 7-51, plus the registers
associated with MSI/MSI-X signaling. Table 7-50 lists the use of the registers in legacy mode and
Table 7-50 lists the use of the registers when using the extended interrupts functionality
7.3.3.1 Interrupt Cause Register (ICR)
7.3.3.1.1 Legacy Mode
In Legacy mode, ICR is used as the sole interrupt cause register. Upon reception of an interrupt, the
interrupt handling routine can read this register in order to find out what are the causes of this
interrupt.
Table 7-50. Interrupt Registers - Legacy Mode
Register Acronym Function
Interrupt Cause ICR Records interrupt conditions.
Interrupt Cause Set ICS Allows software to set bits in the ICR.
Interrupt Mask Set/Read IMS Sets or reads bits in the interrupt mask.
Interrupt Mask Clear IMC Clears bits in the interrupt mask.
Interrupt Acknowledge Auto-
mask
IAM
Under some conditions, the content of this register is copied to the mask
register following read or write of ICR.
Table 7-51. Interrupt Registers - Extended Mode
Register Acronym Function
Extended Interrupt Cause EICR
Records interrupt causes from receive and transmit queues. An interrupt
is signaled when unmasked bits in this register are set.
Extended Interrupt Cause Set EICS Allows software to set bits in the Interrupt Cause register.
Extended Interrupt Mask Set/
Read
EIMS Sets or read bits in the interrupt mask.
Extended Interrupt Mask Clear EIMC Clears bits in the interrupt mask.
Extended Interrupt Auto Clear EIAC
Allows bits in the EICR to be cleared automatically following an MSI-X
interrupt without a read or write of the EICR.
Extended Interrupt
Acknowledge Auto-mask
EIAM
This register is used to decide which masks are cleared in the extended
mask register following read or write of EICR or which masks are set
following a write to EICS. In MSI-X mode, this register also controls which
bits in EIMC are cleared automatically following an MSI-X interrupt.
Interrupt Cause ICR
Records interrupt conditions for special conditions - a single interrupt from
all the conditions of ICR is reflected in the “other” field of the EICR.
Interrupt Cause Set ICS Allows software to set bits in the ICR.
Interrupt Mask Set/Read IMS Sets or reads bits in the other interrupt mask.
Interrupt Mask Clear IMC Clears bits in the Other interrupt mask.
Interrupt Acknowledge Auto-
mask
IAM
Under some conditions, the content of this register is copied to the mask
register following read or write of ICR.
General Purpose Interrupt
Enable
GPIE Controls different behaviors of the interrupt mechanism.