Data Sheet

Inline Functions—Ethernet Controller I210
323
• The IVAR_MISC register maps a TCP timer and other events to 2 MSI-X vectors
Figure 7-14 shows the allocation process.
Table 7-49 lists which interrupt cause is represented by each entry in the MSI-X Allocation registers.
The software has access to 10 mapping entries to map each cause to one of the 5 MSI-x vectors.
Figure 7-14. Cause Mapping in MSI-X Mode
Table 7-49. Cause Allocation in the IVAR Registers
Interrupt Entry Description
Rx_i
INT_Alloc[2*i] (i =
0..3)
Receive queues i - Associates an interrupt occurring in the RX queue i with a corresponding
entry in the MSI-X Allocation registers.
Tx_i
INT_Alloc[2*i+1]
(i = 0..3)
Transmit queues i- Associates an interrupt occurring in the TX queues i with a
corresponding entry in the MSI-X Allocation registers.
TCP timer INT_Alloc[8]
TCP Timer - Associates an interrupt issued by the TCP timer with a corresponding entry in
the MSI-X Allocation registers.
Other cause INT_Alloc[9]
Other causes - Associates an interrupt issued by the other causes with a corresponding
entry in the MSI-X Allocation registers.
IVAR
0
24
31
0
Interrupt causes
(queues)
MSI-X
Vector
3
EICR
Interrupt causes (Other)
IVAR_Misc
RSV
MSI-X
Vector