Data Sheet

Ethernet Controller I210 —Inline Functions
322
•The EICR[31] bit is allocated to the other interrupt causes summarized in the ICR register.
• A single interrupt vector is provided.
Table 7-48 lists the different interrupt causes into the IVAR registers.
7.3.2.2 MSI-X Mode
In MSI-X mode the I210 can request up to 5 vectors.
In MSI-X mode, an interrupt cause is mapped into an MSI-X vector. This section describes the mapping
of interrupt causes, like a specific RX queue event or a Link Status Change event, to MSI-X vectors.
Mapping is accomplished through the IVAR register. Each possible cause for an interrupt is allocated an
entry in the IVAR, and each entry in the IVAR identifies one MSI-X vector. It is possible to map multiple
interrupt causes into the same MSI-X vector.
The EICR also reflects interrupt vectors. The EICR bits allocated for queue causes reflect the MSI-X
vector (bit 2 is set when MSI-X vector 2 is used). Interrupt causes related to non-queue causes are
mapped into the ICR (as in the legacy case). The MSI-X vector for all such causes is reflected in the
EICR.
The following configuration and parameters are involved:
• The IVAR[3:0] registers map 4 Tx queues and 4 Rx queues events to up to 23 interrupt vectors
Figure 7-13. Cause Mapping in Legacy Mode
Table 7-48. Cause Allocation in the IVAR Registers - MSI and Legacy Mode
Interrupt Entry Description
Rx_i
INT_Alloc[2*i] (i =
0..3)
Receive queues i - Associates an interrupt occurring in the Rx queue i with a corresponding
bit in the EICR register.
Tx_i
INT_Alloc[2*i+1]
(i = 0..3)
Transmit queues i- Associates an interrupt occurring in the Tx queue i with a corresponding
bit in the EICR register.
Cause 0
Cause 7
RSV
Single Vector
Other
TCP timer
.
.
.
0
30
31
Queue
Related
causes
Other
causes
IVAR[0]
IVAR[1]
IVAR[2]
IVAR[3]
ICR
EICR
Reflect
Causes
7