Data Sheet

Inline Functions—Ethernet Controller I210
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7.3.1.1 MSI-X and Vectors
MSI-X defines a separate optional extension to basic MSI functionality. Compared to MSI, MSI-X
supports a larger maximum number of vectors, the ability for software to control aliasing when fewer
vectors are allocated than requested, plus the ability for each vector to use an independent address and
data value, specified by a table that resides in Memory Space. However, most of the other
characteristics of MSI-X are identical to those of MSI. For more information on MSI-X, refer to the PCI
Local Bus Specification, Revision 3.0.
MSI-X maps each of the I210 interrupt causes into an interrupt vector that is conveyed by the I210 as
a posted-write PCIe transaction. Mapping of an interrupt cause into an MSI-X vector is determined by
system software (a device driver) through a translation table stored in the MSI-X Allocation registers.
Each entry of the allocation registers defines the vector for a single interrupt cause.
7.3.2 Mapping of Interrupt Causes
There are 10 extended interrupt causes that exist in the I210:
1. 8 traffic causes — 4 Tx, 4 Rx.
2. TCP timer
3. Other causes — Summarizes legacy interrupts into one extended cause.
The way the I210 exposes causes to the software is determined by the interrupt mode described in the
text that follows.
Mapping of interrupts causes is different in each of the interrupt modes and is described in the following
sections of this chapter.
Note: If only one MSI-X vector is allocated by the operating system, then the driver might use the
non MSI-X mapping method even in MSI-X mode.
7.3.2.1 Legacy and MSI Interrupt Modes
In legacy and MSI modes, an interrupt cause is reflected by setting a bit in the EICR register. This
section describes the mapping of interrupt causes, like a specific Rx queue event or a Link Status
Change event, to bits in the EICR register.
Mapping of queue-related causes is accomplished through the IVAR register. Each possible queue
interrupt cause (each Rx or Tx queue) is allocated an entry in the IVAR, and each entry in the IVAR
identifies one bit in the EICR register among the bits allocated to queue interrupt causes. It is possible
to map multiple interrupt causes into the same EICR bit.
In this mode, different queue related interrupt causes can be mapped to the first 4 bits of the EICR
register.
Interrupt causes related to non-queue causes are mapped into the ICR legacy register; each cause is
allocated a separate bit. The sum of all causes is reflected in the Other Cause bit in EICR. Figure 7-13
shows the allocation process.
The following configuration and parameters are involved:
• The IVAR[3:0] entries map 4 Tx queues and 4 Rx queues into the EICR[3:0] bits.
• The IVAR_MISC that maps non-queue causes is not used.
•The EICR[30] bit is allocated to the TCP timer interrupt cause.