Data Sheet
Inline Functions—Ethernet Controller I210
319
Else Credit = Credit + IdleSlope
Note: During QavMode TIPG register value should not be modified from its default value of total 12
bytes IPG between packets.
7.2.7.5.3 Launch Time/Fetch Time Decision
Launch time and Fetch time criteria is defined to be “pass” if either:
• The Launch time/Fetch time match exactly the relevant portion of SYSTIML value
— It is compared against SYSTIML[29:5], and provides transmission granularity of 0.032 µs
• The time passed from (post) Launch time/Fetch time in the SYSTIML is within the allowed Launch
time/Fetch time criteria
— The Allowed Fetch time and Allowed Launch time should be calculated such that it is allowed to
Fetch/Transmit a packet if the current time is within Fetch/Launch time + 0.5 second.
— Note that the SYSTIML register max value is 999,999,999 dec (0x3B9AC9FF) and it wraps to 0
when reaching this value (representing a full second).
7.2.7.6 Qav Latency
The latency between transmission scheduling (either credit base or launch time) and the time the
packet is transmitted to the network is listed in Table 7-62.
7.2.7.7 Qav Configuration
Context Descriptor Configuration
LaunchTime (25 bits (56:32) based on SYSTIM)
Global Qav configuration:
TXPBSIZE.Tx0pbsize/Tx1pbsize/Tx2pbsize/Tx3pbsize (Tx packet buffer size assignment)
• Recommended configuration is 8KB for PB0, PB1 and 4KB for PB2, PB3
RXPBSIZE.Rxpbsize (Rx packet buffer size assignment)
• To comply with the Tx recommendation above need to set to 0x20 (32 KB). Refer to the setting rule
defined in Section 4.5.9.
DTXMXPKTSZ.MAX_TPKT_SIZE (DMA Tx maximum packet size)
Table 7-47. Packet Scheduling to its Transmission Latency
Link Speed
Latency between launch time and packet in the MAC (the time on which packet 1588
time stamping is taken). For a complete delay from between launch time and SFD on
the PHY MDI pins, please add the latency defined in Table 7-62 (delay between packet
timestamp and SFD on the MDI pins)
Min Max Comments
Transmit at 10 Mb/s Not measured Assume no interfering
transmission (see also
SP_WAIT_SR setting).
The min/max values represent
possible jitter.
In case of no concurrent
receive, the jitter is reduced by
16 ns.
Transmit at 100 Mb/s 1.184 µs 1.360 µs
Transmit at 1 Gb/s 288 ns 304 ns