Data Sheet

Ethernet Controller I210 —Inline Functions
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2. The WB_on_EITR bit enables head write upon EITR expiration. When Head write back operation is
enabled (TDWBAL[n].Head_WB_En = 1) setting the TDWBAL[n].WB_on_EITR bit to 1b enables
placing an upper limit on delay of head write-back operation.
The 30 upper bits of the TDWBAL[n] register hold the lowest 32 bits of the head write-back address,
assuming that the two last bits are zero. The TDWBAH[n] register holds the high part of the 64-bit
address.
Note: Hardware writes a full Dword when writing this value, so software should reserve enough
space for each head value.
If software enables Head Write-Back, it must also disable PCI Express Relaxed Ordering on
the write-back transactions. This is done by disabling bit 11 in the TXCTL register for each
active transmit queue. See Section 8.13.2.
The I210 might update the Head with values that are larger then the last Head pointer, which
holds a descriptor with the RS bit set; however, the value always points to a free descriptor
(descriptor that is not longer owned by the I210).
Note: Software should program TDWBAL[n], TDWBAH[n] registers when queue is disabled
(TXDCTL[n].Enable = 0).
7.2.4 TCP/UDP Segmentation
Hardware TCP segmentation is one of the offloading options supported by the Windows* and Linux*
TCP/IP stack. This is often referred to as TCP Segmentation Offloading or TSO. This feature enables the
TCP/IP stack to pass to the network device driver a message to be transmitted that is bigger than the
Maximum Transmission Unit (MTU) of medium. It is then the responsibility of the software device driver
and hardware to divide the TCP message into MTU size frames that have appropriate layer 2 (Ethernet),
3 (IP), and 4 (TCP) headers. These headers must include sequence number, checksum fields, options
and flag values as required. Note that some of these values (such as the checksum values) are unique
for each packet of the TCP message and other fields such as the source IP address are constant for all
packets associated with the TCP message.
The I210 supports also UDP segmentation for embedded applications, although this offload is not
supported by the regular Windows* and Linux* stacks. Any reference in this section to TCP
segmentation, should be considered as referring to both TCP and UDP segmentation.
Padding (TCTL.PSP) must be enabled in TCP segmentation mode, since the last frame might be shorter
than 60 bytes, resulting in a bad frame if PSP is disabled.
The offloading of these mechanisms from the software device driver to the I210 saves significant CPU
cycles. Note that the software device driver shares the additional tasks to support these options.
7.2.4.1 Assumptions
The following assumptions apply to the TCP segmentation implementation in the I210:
•The RS bit operation is not changed.
• Interrupts are set after data in buffers pointed to by individual descriptors is transferred (DMA'd) to
hardware.
7.2.4.2 Transmission Process
The transmission process for regular (non-TCP segmentation packets) involves:
• The protocol stack receives from an application a block of data that is to be transmitted.