Data Sheet
Revision History—Ethernet Controller I210
3
Revision History
Rev Date Notes
3.3 June 2018
Updated Section 7.2.2.2.3 [LaunchTime (25)]
3.2 January 2018
Updated Table 2-1 (Pull-Up/Pull-Down Resistors).
Added section 3.3.2.4 (iNVM Structure Version Information).
Updated section 5.5.6 (Timing Guarantees).
Updated section 6.8.2 (Port Identification LED Blinking; Word 0x04).
Updated section 11.8.1 (Flash Parts).
3.1 June 2017
Revised Section:
• 3.4.3 (iNVM Programming Flows).
3.0 March 2017
Revised Sections:
• 3.7.8.5.7 (Internal PHY Power-Down State).
• 11.6.2.7 (MDIO AC Specification).
• 12.4 (Oscillator Support).
• 12.11 (XOR Testing).
2.9 January 2016
• Revised Table 2-1 (changed JTAG_CLK to show a pull down resistor instead of a pull up).
• Updated intra-document cross references.
• Revised the description of Section 7.8.3.3.3 (Synchronized Output Clock on SDP Pins).
• Revised Section 8.15.13 (TimeSync Auxiliary Control Register - TSAUXC (0xB640; RW), bit 4
and bit 7 description).
2.8 September 2015
• Revised Section 6.8.7.2 (added image build information).
• Updated Table 11-11 (t
DS
and t
DH
descriptions).
• Updated Table 11-15 (c
load
value).
• Updated Figure 12.12 (changed pull-up value from 1.9 to 1.5).
• Updated Section 12.5.4 (Diff to CMR value).
• Added Section 12.5.6.5 (Maximum Trace Lengths Based on Trace Geometry).
• Fixed cross references in Section 12.6.
2.7 February 2015
• Removed all references to IEEE Std 1149.6-2003, IEEE Standard for Boundary-Scan Testing of
Advanced Digital Networks, IEEE, 2003.
• Updated section 8.27.3.37 (Misc Test - Page 6, Register 26).
• Removed sections 8.27.3.38 through 8.27.3.43.
• Updated section 12-4 (Oscillator Support).
• Added section 12.5.5 (Designing the I210 as a 10/100 Mb/s Only Device).
• Updated section 12.5.6.4 (Differential Pair Trace Routing for 10/100/1000 Designs).
2.6 June 2014
• Revised section 11.8.1 (replaced W25Q16DWSSIG with W25Q16DVSSIG).
2.5 February 2014
• Replaced figure 2-2.
• Revised section 3.4 (iNVM).
• Revised section 3.4.2 (iNVM Structures).
• Revised section 3.7.8.5.5.1 (Internal PHY Back-to-Back SPD).
• Revised table 8-6 (Register Summary; PQMPRC[0 - 3]).
• Revised table 11-11 (Flash I/F Timing Parameters).
• Revised table 11-17 (Specification for External Clock Oscillator).
2.4 July 2013
• Updated revision history.
•
•
•
•
•
•
•
•