Data Sheet

Inline Functions—Ethernet Controller I210
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For the first condition, write-backs are immediate. This is the default operation and is backward
compatible with previous Intel Ethernet controllers.
The other two conditions are only valid if descriptor bursting is enabled (Section 8.12.15). In the
second condition, the EITR counter is used to force timely write-back of descriptors. The first packet
after timer initialization starts the timer. Timer expiration flushes any accumulated descriptors and sets
an interrupt event (TXDW).
For the last condition, if TXDCTL[n].WTHRESH descriptors are ready for write-back, the write-back is
performed.
An additional mode in which transmit descriptors are not written back at all and the head pointer of the
descriptor ring is written instead as described in Section 7.2.3.
Note: When transmit ring is smaller than internal cache size (24 descriptors) then at least one full
packet should be placed in the ring and TXDCTL[n].WTHRESH value should be less than ring
size. If TXDCTL[n].WTHRESH is 0x0 (transmit RS mode) then at least one descriptor should
have the RS bit set inside the ring.
7.2.3 Transmit Completions Head Write Back
In legacy hardware, transmit requests are completed by writing the DD bit to the transmit descriptor
ring. This causes cache thrash since both the software device driver and hardware are writing to the
descriptor ring in host memory. Instead of writing the DD bits to signal that a transmit request
completed, hardware can write the contents of the descriptor queue head to host memory. The
software device driver reads that memory location to determine which transmit requests are complete.
In order to improve the performance of this feature, the software device driver might program DCA
registers to configure which CPU is processing each TX queue to allow pre-fetching of the head write
back value from the right cache.
7.2.3.1 Description
The head counter is reflected in a memory location that is allocated by software, for each queue.
Head write back occurs if TDWBAL[n].Head_WB_En is set for this queue and the RS bit is set in the Tx
descriptor, following corresponding data upload into packet buffer. If the head write-back feature is
enabled, the I210 ignores TXDCTL[n].WTHRESH and takes in account only descriptors with the RS bit
set (as if the TXDCTL[n].WTHRESH field was set to 0x0). In addition, the head write-back occurs upon
EITR expiration for queues where the WB_on_EITR bit in TDWBAL[n] is set.
Software can also enable coalescing of the head write-back operations to reduce traffic on the PCIe bus,
by programming the TXDCTL.HWBTHRESH field to a value greater than zero. In this case, head write-
back operation occurs only after the internal pending write-back count is greater than the
TXDCTL[n].HWBTHRESH value.
The software device driver has control on this feature through Tx queue 0-3 head write-back address,
low (TDWBAL[n]) and high (TDWBAH[n]) registers thus supporting 64-bit address access. See registers
description in Section 8.12.16 and Section 8.12.17.
The 2 low register's LSB bits of the TDWBAL[n] register hold the control bits.
1. The Head_WB_En bit enables activation of the head write back feature. When
TDWBAL[n].Head_WB_En is set to 1 no TX descriptor write-back is executed for this queue.