Data Sheet

Ethernet Controller I210 —Inline Functions
298
The shaded boxes in the figure represent descriptors that are not currently owned by hardware that
software can modify.
The transmit descriptor ring is described by the following registers:
• Transmit Descriptor Base Address register (TDBA 0-3):
This register indicates the start address of the descriptor ring buffer in the host memory; this 64-bit
address is aligned on a 16-byte boundary and is stored in two consecutive 32-bit registers.
Hardware ignores the lower four bits.
• Transmit Descriptor Length register (TDLEN 0-3):
This register determines the number of bytes allocated to the circular buffer. This value must be
zero modulo 128.
• Transmit Descriptor Head register (TDH 0-3):
This register holds a value that is an offset from the base and indicates the in-progress descriptor.
There can be up to 64 KB descriptors in the circular buffer. Reading this register returns the value of
head corresponding to descriptors already loaded in the output FIFO. This register reflects the
internal head of the hardware write-back process including the descriptor in the posted write pipe
and might point further ahead than the last descriptor actually written back to the memory.
• Transmit Descriptor Tail register (TDT 0-3):
This register holds a value, which is an offset from the base, and indicates the location beyond the
last descriptor hardware can process. This is the location where software writes the first new
descriptor.
The driver should not handle to the I210 descriptors that describe a partial packet. Consequently,
the number of descriptors used to describe a packet can not be larger than the ring size.
Figure 7-10. Transmit Descriptor Ring Structure
Circular Buffer
Head
Base + Size
Base
Transmit
Queue
Tail