Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express

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Ethernet Controller I210 —Inline Functions

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7.2.2.3 Advanced Transmit Data Descriptor

Note: For frames that span multiple descriptors, all fields apart from DCMD.EOP, DCMD.RS,

DCMD.DEXT, DTALEN, Address and DTYP are valid only in the first descriptor and are ignored

in the subsequent ones.

7.2.2.3.1 Address (64) / DMA Time Stamp

Address: Physical address of a data buffer in host memory that contains a portion of a transmit packet

provided by the software.

DMA Time Stamp: When enabled by the 1588_STAT_EN flag in the TQAVCTRL register, the DMA Time

Stamp is valid and the TS_STAT flag in the STA field is set. Otherwise, this field is undefined and the

TS_STAT flag in the STA field is cleared. The DMA Time Stamp reports the time on which the descriptor

is written back to host memory. In order to minimize the time gap between DMA completion and

descriptor write back, the software could either use the RS bit or set the WTHRESH parameter in the

TXDCTL[n] register (of the queue) to zero. The DMA Time Stamp only part of the time (in the SYSTIM

registers) as follows. Therefore, the software should read the SYSTIMH register (once every ~512 sec)

in order to keep track of the complete time.

• DMA Time Stamp bits 31:0 get the value of SYSTIML register

• DMA Time Stamp bits 41:32 get the value of the 10 LS bits of the SYSTIMH register

• DMA Time Stamp bits 63:42 are set to zero

7.2.2.3.2 DTALEN (16)

Length in bytes of data buffer at the address pointed to by this specific descriptor.

Note: If the TCTL.PSP bit is set, the total length of the packet transmitted, not including FCS, should

be at least 17 bytes. If bit is cleared the total length of the packet transmitted, not including

FCS should be at least 60 bytes.

Note: The maximum allowable packet size for transmits is based on the value written to the DMA TX

Max Allowable packet size (DTXMXPKTSZ) register. Default value is 9,728 bytes.

Table 7-33. Advanced Transmit Data Descriptor (TDESD) Layout - (Type = 0011b)

0 Address[63:0]

8PAYLEN POPTSRSV

IDX STA DCMD DTYP MAC RSV

1. RSV - Reserved

DTALEN

63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0

Table 7-34. Advanced Tx Descriptor Write-back Format

0DMA Time Stamp

8 Reserved STA Reserved

63 36 35 32 31 0