Data Sheet

Inline Functions—Ethernet Controller I210
275
For applications where the latency of received packets is more important than the bus efficiency and
the CPU utilization, an EITR value of zero can be used. In this case, each receive descriptor are written
to the host immediately. If RXDCTL[n].WTHRESH equals zero, then each descriptor are written back
separately;, otherwise, write back of descriptors can be coalesced if descriptor accumulates in the
internal descriptor ring due to bandwidth constrains.
All write-back decisions are based on the number of descriptors available and do not take into account
any split of the transaction due to bus access limitations.
7.1.4.5 Receive Descriptor Ring Structure
Figure 7-7 shows the structure of each of the 4 receive descriptor rings. Hardware maintains 4 circular
queues of descriptors and writes back used descriptors just prior to advancing the head pointer(s).
Head and tail pointers wrap back to base when size descriptors have been processed.
Figure 7-7. Receive Descriptor Ring Structure
Circular Buffer Queues
Head
Base + Size
Base
Receive
Queue
Tail