Data Sheet

Ethernet Controller I210 —Inline Functions
274
VLAN Tag (16)
These bits are described in the legacy descriptor format in Section 7.1.4.
7.1.4.3 Receive Descriptor Fetching
The fetching algorithm attempts to make the best use of PCIe bandwidth by fetching a cache-line (or
more) descriptor with each burst. The following paragraphs briefly describe the descriptor fetch
algorithm and the software control provided.
When the RXDCTL[n].ENABLE bit is set and the on-chip descriptor cache is empty, a fetch happens as
soon as any descriptors are made available (Host increments the RDT[n] tail pointer). When the on-
chip buffer is nearly empty (defined by RXDCTL.PTHRESH), a prefetch is performed each time enough
valid descriptors (defined by RXDCTL.HTHRESH) are available in host memory.
When the number of descriptors in host memory is greater than the available on-chip descriptor cache,
the I210 might elect to perform a fetch that is not a multiple of cache-line size. Hardware performs this
non-aligned fetch if doing so results in the next descriptor fetch being aligned on a cache-line boundary.
This enables the descriptor fetch mechanism to be more efficient in the cases where it has fallen behind
software.
All fetch decisions are based on the number of descriptors available and do not take into account any
split of the transaction due to bus access limitations.
7.1.4.4 Receive Descriptor Write-back
Processors have cache-line sizes that are larger than the receive descriptor size (16 bytes).
Consequently, writing back descriptor information for each received packet would cause expensive
partial cache-line updates. A receive descriptor packing mechanism minimizes the occurrence of partial
line write-backs.
To maximize memory efficiency, receive descriptors are packed together and written as a cache-line
whenever possible. Descriptors write-backs accumulate and are opportunistically written out in cache
line-oriented chunks, under the following scenarios:
• RXDCTL[n].WTHRESH descriptors have been used (the specified maximum threshold of unwritten
used descriptors has been reached).
• The receive timer expires (EITR) - in this case all descriptors are flushed ignoring any cache-line
boundaries.
• Explicit software flush (RXDCTL.SWFLS).
• Dynamic packets - if at least one of the descriptors that are waiting for write-back are classified as
packets requiring immediate notification the entire queue is flushed out.
When the number of descriptors specified by RXDCTL[n].WTHRESH have been used, they are written
back regardless of cache-line alignment. It is therefore recommended that RXDCTL[n].WTHRESH be a
multiple of cache-line size. When the receive timer (EITR) expires, all used descriptors are forced to be
written back prior to initiating the interrupt, for consistency. Software might explicitly flush
accumulated descriptors by writing the RXDCTL[n] register with the SWFLS bit set.
When the I210 does a partial cache-line write-back, it attempts to recover to cache-line alignment on
the next write-back.