Data Sheet

Ethernet Controller I210 —Inline Functions
268
IPE/L4E
The IP and TCP/UDP checksum error bits from Table 7-7 are valid only when the IPv4 or TCP/UDP
checksum(s) is performed on the received packet as indicated via IPCS and L4CS. These, along with the
other error bits, are valid only when the EOP and DD bits are set in the descriptor.
Note: Receive checksum errors have no effect on packet filtering.
If receive checksum offloading is disabled (RXCSUM.IPOFLD and RXCSUM.TUOFLD), the IPE and L4E
bits are 0b.
RXE
The RXE error bit is asserted in the following case:
1. CRC error is detected. CRC can be a result of reception of /V/ symbol on the TBI interface (see
section 3.7.3.3.2) or assertion of RxERR on the MII/GMII interface or bad EOP or lose of sync
during packet reception. Packets with a CRC error are posted to host memory only when store-bad-
packet bit (RCTL.SBP) is set.
VLAN Tag Field (16)
Hardware stores additional information in the receive descriptor for 802.1Q packets. If the packet type
is 802.1Q (determined when a packet matches VET and CTRL.VME = 1b), then the VLAN Tag field
records the VLAN information and the four-byte VLAN information is stripped from the packet data
storage. Otherwise, the VLAN Tag field contains 0x0000. The rule for VLAN tag is to use network
ordering (also called big endian). It appears in the following manner in the descriptor:
7.1.4.2 Advanced Receive Descriptors
7.1.4.2.1 Advanced Receive Descriptors (RDESC) - Read Format
Table 7-9 shows the receive descriptor. This is the format that software writes to the descriptor queue
and hardware reads from the descriptor queue in host memory. Hardware writes back the descriptor in
a different format, shown in Table 7-10.
Packet Buffer Address (64) - Physical address of the packet buffer. The lowest bit is either A0 (LSB
of address) or NSE (No-Snoop Enable), depending on bit RXCTL.RXdataWriteNSEn of the relevant
queue. See Section 8.13.1.
Header Buffer Address (64) - Physical address of the header buffer. The lowest bit is DD.
Table 7-8. VLAN Tag Field Layout (for 802.1Q Packet)
15 13 12 11 0
PRI CFI VLAN
Table 7-9. RDESC Descriptor Read Format
63 10
0 Packet Buffer Address [63:1] A0/NSE
8 Header Buffer Address [63:1] DD