Data Sheet

Inline Functions—Ethernet Controller I210
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If SRRCTL[n].BSIZEPACKET is set to zero for any queue, the buffer size defined by RCTL.BSIZE is used.
Otherwise, the buffer size defined by SRRCTL[n].BSIZEPACKET is used.
If the receive buffer size is selected by bit settings in the Receive Control (RCTL.BSIZE) buffer sizes of
256, 512, 1024, and 2048 bytes are supported.
If the receive buffer size is selected by SRRCTL[n].BSIZEPACKET, buffer sizes of 1KB to 127 KB are
supported with a resolution of 1 KB.
In addition, for advanced descriptor usage the SRRCTL.BSIZEHEADER field is used to define the size of
the buffers allocated to headers. Header Buffer sizes of 64 bytes to2048 bytes with a resolution of 64
bytes are supported.
The I210 places no alignment restrictions on receive memory buffer addresses. This is desirable in
situations where the receive buffer was allocated by higher layers in the networking software stack, as
these higher layers might have no knowledge of a specific device's buffer alignment requirements.
Note: When the No-Snoop Enable bit is used in advanced descriptors, the buffer address is 16-bit
(2-byte) aligned.
7.1.3.2 On-Chip Receive Buffer
The I210 allocates by default a 36 KB on-chip packet buffer. The buffer is used to store packets until
they are forwarded to the host. Actual on-chip receive buffer allocated can be controlled the RXPBSIZE
register.
7.1.3.3 On-chip Descriptor Buffers
The I210 contains a 16 descriptor cache for each receive queue used to reduce the latency of packet
processing and to optimize the usage of PCIe bandwidth by fetching and writing back descriptors in
bursts. The fetch and write-back algorithm are described in Section 7.1.4.3 and Section 7.1.4.4.
7.1.4 Receive Descriptors
7.1.4.1 Legacy Receive Descriptor Format
A receive descriptor is a data structure that contains the receive data buffer address and fields for
hardware to store packet information. If SRRCTL[n].DESCTYPE = 000b, the I210 uses the legacy
Receive descriptor listed in Table 7-3. The shaded areas indicate fields that are modified by hardware
upon packet reception (so-called descriptor write-back).
After receiving a packet for the I210, hardware stores the packet data into the indicated buffer and
writes the length, packet checksum, status, errors, and status fields.
Packet Buffer Address (64) - Physical address of the packet buffer.
Table 7-3. Legacy Receive Descriptor (RDESC) Layout
63 48 47 40 39 32 31 16 15 0
0 Buffer Address [63:0]
8
VLAN Tag Errors Status Fragment Checksum Length