Data Sheet

Pin Interface—Ethernet Controller I210
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2.3.3 System Management Bus (SMBus) Interface
Note: If the SMBus is disconnected, an external pull-up should be used for these pins, unless it is
guaranteed that manageability is disabled in the I210.
2.3.4 NC-SI and Testability
Table 2-4. SMBus Interface
Symbol Reserved Lead # Type Op Mode Name and Function
SMB_DATA 36 T/s, o/d Bi-dir
SMBus Data.
Stable during the high period of the clock (unless
it is a start or stop condition).
SMB_CLK 34 T/s, o/d Bi-dir
SMBus Clock.
One clock pulse is generated for each data bit
transferred.
SMB_ALRT_N 35 T/s, o/d Output
SMBus Alert.
Acts as an interrupt pin of a slave device on the
SMBus in pass-through mode.
Table 2-5. NC-SI and Testability
Symbol Reserved Lead # Type
Op
Mode
Name and Function
NC_SI_CLK_IN 2 NCSI_in Input
NC-SI Reference Clock Input.
Synchronous clock reference for receive, transmit, and
control interface. This signal is a 50 MHz clock +/- 100 ppm.
NC_SI_CRS_DV 3 NCSI_out Output NC-SI Carrier Sense/Receive Data Valid (CRS/DV).
NC_SI_RXD0 6 NCSI_out Output
NC-SI Receive Data 0.
Data signals to the Manageability Controller (MC).
NC_SI_RXD1 5 NCSI_out Output
NC-SI Receive Data 1.
Data signals to the MC.
NC_SI_TX_EN 7 NCSI_in Input
NC-SI Transmit Enable.
NC_SI_TXD0 9 NCSI_in Input
NC-SI Transmit Data 0.
Data signals from the MC.
NC_SI_ARB_IN 43 NC-SI-in Input
NC-SI hardware arbitration token output pin.
NC_SI_ARB_OUT 44 NC-SI-out Output
NC-SI hardware arbitration token input pin.
NC_SI_TXD1 8 NCSI_in Input
NC-SI Transmit Data 1.
Data signal from the MC.
JTAG_TDI 29 In Input JTAG TDI Input.
JTAG_CLK 19 In Input JTAG Clock Input.
JTAG_TMS 18 In Input
JTAG Test Mode Select.
This input controls the transitions of the test interface state
machine.
JTAG_TDO 4 O/D JTAG TDO