Data Sheet

Ethernet Controller I210 —Pin Interface
24
2.3.1 PCIe
2.3.2 Flash
Table 2-2. PCIe
Symbol Reserved Lead # Type
Op
Mode
Name and Function
PECLKp
PECLKn
26
25
A-in Input
PCIe Differential Reference Clock In
This pin receives a 100 MHz differential clock input. This clock
is used as the reference clock for the PCIe Tx/Rx circuitry and
by the PCIe core PLL to generate a 125 MHz clock and
250 MHz clock for the PCIe core logic.
PE_Tp
PE_Tn
21
20
A-out Output
PCIe Serial Data Output
Serial differential output link in the PCIe interface running at
2.5 Gb/s. This output carries both data and an embedded
2.5 GHz clock that is recovered along with data at the
receiving end.
PE_Rp
PE_Rn
24
23
A-in Input
PCIe Serial Data Input
Serial differential input link in the PCIe interface running at
2.5 Gb/s. The embedded clock present in this input is
recovered along with the data.
PE_WAKE_N 16 T/s Bi-dir
Wake
The I210 drives this signal to zero when it detects a wake-up
event and either:
• The PME_en bit in PMCSR is 1b or
• The APME bit of the Wake Up Control (WUC) register is
1b.
In OBFF mode
, OBFF events are signaled using the
PE_WAKE_N pin.
PE_RST_N 17 In Input
Power and Clock Good Indication
The PE_RST_N signal indicates that both PCIe power and
clock are available.
Table 2-3. Flash
Symbol Reserved Lead # Type
Op
Mode
Name and Function
NVM_SI 12 T/s Output
Serial Data Output
Connect this lead to the input of the Flash.
NVM_SO 14 T/s Input
Serial Data Input
Connect this lead to the output of the Flash.
NVM_SK 13 T/s Output
Non-Volatile Memory Serial Clock
NVM_CS_N 15 T/s Output
Non-Volatile Memory Chip Select Output