Data Sheet

Ethernet Controller I210 —Flash Map
230
6.7.8.1.1 PHY Configuration Section Length - Offset 0x0
The section length word contains the length of the section in words. Note that section length count does
not include the section length word and Block CRC8 word.
6.7.8.1.2 Block CRC8 (Offset 0x1)
6.7.8.1.3 PHY Number and PHY Register Address - (Offset 2*n; [n = 1... Section Length])
Table 6-8. PHY Auto Configuration Structure Format
Offset High Byte[15:8] Low Byte[7:0] Section
0x0 Section length = 2*n (n – number of registers to configure) Section 6.7.8.1.1
0x1 Block CRC8. Section 6.7.8.1.2
0x2 PHY number and PHY register address. Section 6.7.8.1.3
0x3 PHY data (MDIC[15:0] or I2CCMD[15:0]). Section 6.7.8.1.4
…
2*n PHY number and PHY register address Section 6.7.8.1.3
2*n + 1 PHY data (MDIC[15:0] or I2CCMD[15:0]) Section 6.7.8.1.4
Bits Name
Default
HW Mode
Description
15 Reserved
14:0 Section_length Section length in words.
Bit Name Description
15:8 Reserved
7:0 CRC8
CRC8 is computed over the module, header excluded (for example, starting
from word offset 0x2 included).
Bits
Name
Default HW
Mode
Description
15:14 Transaction Interface 00b
Defines the PHY interface to be used for the transaction:
00b - Internal PHY, via MDIC register
01b - External PHY over I2C pins, via MDIC register
10b - External PHY over I2C pins, via I2CCMD register
11b - Reserved
13:9 Reserved 0x0 Reserved
8 Loading Event 0b
Defines the loading event:
0b - PHY resets (including POR).
1b - POR only. This mode is not effective for internal copper PHY settings
as a PHY reset event occurs anyway after boot time.
7:0 PHY Register Address
PHY register address to which the data is written.
See Section 8.2.4 and Section 8.17.8 for information on the MDIC and
I2CCMD registers, respectively.
Note: 5 LSB bits define the register address when access is via the MDIC
register.