Data Sheet

Flash Map—Ethernet Controller I210
229
6.7.7 Traffic Type Parameters – (Global MNG Offset 0xB)
6.7.7.1 Section Header — Offset 0x0
6.7.7.2 Traffic Type Data - Offset 0x1
6.7.8 PHY Configuration Pointer – (Global MNG Offset 0xF)
6.7.8.1 PHY Configuration Structure
This section describes the PHY auto configuration structure used to configure PHY related circuitry. The
programming in this section is made of PHY registers address/data items. Each item includes bits that
define:
• The PHY interface to be used - external/internal, register set, pins
• The loading event - PHY reset or POR only
The PHY Configuration Pointer (Global MNG Offset 0xF) points to the start (offset 0x0) of this type of
structure to configure PHY registers (internal and external PHYs). If pointer is 0xFFFF then no structure
exists.
When the FW has completed the configuration, it is required to move back the PHY interface mode to
the default loaded from Flash in order to avoid an impact on SW driver.
Bits Name
Default
HW Mode
Description Reserved
15:8 Block CRC8
7:0 Block Length 0x1 Section length in words.
Bits Name
Default
HW Mode
Description Reserved
15:2 Reserved Reserved
1:0 Traffic Types
00b = Reserved.
01b = Network to MC traffic only allowed.
10b = OS2BMC traffic only allowed.
11b = Both Network to MC traffic and OS2BMC traffic allowed.
Notes:
1. The traffic types defined by this field are enabled by the
Manageability Mode field and the OS2BMC Capable bit in the
Common Firmware Parameters 1 Flash word (refer to
Section 6.7.1.2).
2. Field loaded to MANC.EN_BMC2NET bit and
MANC.EN_BMC2OS bit (refer to Section 8.22.5).
Bit Name Description
15:0 Pointer
Pointer to PHY configuration structure. Refer to Section 6.7.8.1 for
details of the structure. A value of 0xFFFF means the pointer is
invalid.